Experimental study of gate oxide early-life failures

Large-scale experimental data from 90nm test chips consisting of 49,152 transistors, and experiments on 90nm test chips containing inverter chains are used to establish: 1. A gate-oxide early-life failure (ELF, also called infant mortality) candidate transistor produces gradually degraded drive currents over time; 2. A digital circuit path consisting of a gate-oxide ELF candidate transistor experiences gradual delay shifts over time before the circuit produces functional failures. These results may be utilized to effectively overcome ELF challenges in scaled CMOS technologies.

[1]  Theo J. Powell,et al.  Delta Iddq for testing reliability , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[2]  Edward J. McCluskey,et al.  Very-low-voltage testing for weak CMOS logic ICs , 1993, Proceedings of IEEE International Test Conference - (ITC).

[3]  Chenming Hu,et al.  Hot-Electron-Induced MOSFET Degradation - Model, Monitor, and Improvement , 1985, IEEE Journal of Solid-State Circuits.

[4]  Sandip Kundu,et al.  Trends in manufacturing test methods and their implications , 2004 .

[5]  R.W. Dutton,et al.  Macro-Model for Post-Breakdown 90NM and 130NM Transistors and its Applications in Predicting Chip-Level Function Failure after ESD-CDM Events , 2007, 2007 IEEE International Reliability Physics Symposium Proceedings. 45th Annual.

[6]  Jody Van Horn.  Towards achieving relentless reliability gains in a server marketplace of teraflops, laptops, kilowatts, and "cost, cost, cost"...: making peace between a black art and the bottom line , 2005, ITC.

[7]  E. Vandamme,et al.  Impact of MOSFET gate oxide breakdown on digital circuit operation and reliability , 2000 .

[8]  Edward J. McCluskey,et al.  MINVDD testing for weak CMOS ICs , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

[9]  Claude Thibeault.  An histogram based procedure for current testing of active defects , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[10]  Edward J. McCluskey,et al.  SHOrt voltage elevation (SHOVE) test for weak CMOS ICs , 1997, Proceedings. 15th IEEE VLSI Test Symposium (Cat. No.97TB100125).

[11]  James F. Plusquellic,et al.  Digital integrated circuit testing using transient signal analysis , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[12]  Robert C. Aitken,et al.  Current ratios: a self-scaling technique for production I/sub DDQ/ testing , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[13]  Thomas J. Anderson,et al.  Test connections - tying application to process , 2005, IEEE International Conference on Test, 2005..

[14]  Edward J. McCluskey,et al.  Detecting delay flaws by very-low-voltage testing , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[15]  Serge N. Demidenko,et al.  Reducing burn-in time through high-voltage stress test and Weibull statistical analysis , 2006, IEEE Design & Test of Computers.

[16]  Subhasish Mitra.  Globally Optimized Robust Systems to Overcome Scaled CMOS Reliability Challenges , 2008, 2008 Design, Automation and Test in Europe.

[17]  Shekhar Y. Borkar,et al.  Designing reliable systems from unreliable components: the challenges of transistor variability and degradation , 2005, IEEE Micro.

[18]  A. Vassighi,et al.  Characterizing infant mortality in high volume manufacturing , 2008, 2008 IEEE International Reliability Physics Symposium.

[19]  Subhasish Mitra,et al.  CASP: Concurrent Autonomous Chip Self-Test Using Stored Test Patterns , 2008, 2008 Design, Automation and Test in Europe.

[20]  Florence Azaïs,et al.  Delay testing of MOS transistor with gate oxide short , 2003, 2003 Test Symposium.

[21]  Phil Nigh,et al.  Test method evaluation experiments and data , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[22]  D. M. H. Walker,et al.  I/sub DDQ/ test: will it survive the DSM challenge? , 2002, IEEE Design & Test of Computers.

[23]  E. Vandamme,et al.  Impact of MOSFET oxide breakdown on digital circuit operation and reliability , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[24]  W. Cleveland.  The elements of graphing data , 1986 .

[25]  Subhasish Mitra,et al.  Gate-Oxide Early Life Failure Prediction , 2008, 26th IEEE VLSI Test Symposium (vts 2008).

[26]  Chenming Hu,et al.  Hot-electron-induced MOSFET degradation—Model, monitor, and improvement , 1985, IEEE Transactions on Electron Devices.

[27]  M. Ray Mercer,et al.  Iddq test: sensitivity analysis of scaling , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[28]  Bram Kruseman,et al.  Comparison of I/sub DDQ/ testing and very-low voltage testing , 2002, Proceedings. International Test Conference.

[29]  Anthony C. Miller.  I/sub DDQ/ testing in deep submicron integrated circuits , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[30]  Haihua Yan,et al.  Experiments in detecting delay faults using multiple higher frequency clocks and results from neighboring die , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[31]  J. Stathis,et al.  Dielectric breakdown mechanisms in gate oxides , 2005 .

[32]  Charles F. Hawkins,et al.  IDDQ Testing of VLSI Circuits , 1993, Springer US.

[33]  P. Moran.  Notes on continuous stochastic phenomena. , 1950, Biometrika.

[34]  Young-Kwan Park,et al.  A Unified Compact Model of the Gate Oxide Reliability for Complete Circuit Level Analysis , 2007, 2007 IEEE International Electron Devices Meeting.

[35]  G. Guegan,et al.  Collapse of MOSFET drain current after soft breakdown and its dependence on the transistor aspect ratio W/L , 2003, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..

[36]  H. H. Hoang,et al.  Electromigration early‐failure distribution , 1989 .

[37]  David Turner,et al.  Screening minVDD outliers using feed-forward voltage testing , 2002, Proceedings. International Test Conference.

[38]  G. Ghibaudo,et al.  Review on high-k dielectrics reliability issues , 2005, IEEE Transactions on Device and Materials Reliability.

[39]  Beat Kleiner,et al.  Graphical Methods for Data Analysis , 1983 .

[40]  W. C. Riordan,et al.  Microprocessor reliability performance as a function of die location for a 0.25 /spl mu/, five layer metal CMOS logic process , 1999, 1999 IEEE International Reliability Physics Symposium Proceedings. 37th Annual (Cat. No.99CH36296).

[41]  Adit D. Singh,et al.  Burn-in failures and local region yield: an integrated field-reliability model , 2001, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001.

[42]  W. Robert Daasch,et al.  Statistical post-processing at wafersort-an alternative to burn-in and a manufacturable solution to test limit setting for sub-micron technologies , 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).

[43]  Wojciech Maly,et al.  Current signatures [VLSI circuit testing] , 1996, Proceedings of 14th VLSI Test Symposium.

[44]  Russell B. Miller,et al.  Unit level predicted yield: a method of identifying high defect density die at wafer sort , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).