Gambit: A Tool for the Simultaneous Placement and Detailed Routing of Gate-Arrays

In this paper we present a new method of integrating the placement and routing stages in the physical design of channel-based architectures, and present the first implementation of this method: Gambit. Based on a graphcolorin g representation of the routing problem, we are able to produce circuit placements and detailed routes simultaneously, allowing routing constraints to influence decisions made in creating the placement. Gambit produces circuit mappings for boths tandard and three-dimensional FPGA architectures, and serves primarily as a proof-of-concept: the proposed algorithm will simultaneously perform placement and detailed routing for channel-based architectures. While the quality of Gambit mappings are not yet competitive withs tate-of-theart tools in the literature, experimental results indicate that it does have the potential to become so.

[1]  Gabriel Robins,et al.  New performance-driven FPGA routing algorithms , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Joseph L. Ganley,et al.  Performance-oriented placement and routing for field-programmable gate arrays , 1995, Proceedings of EURO-DAC. European Design Automation Conference.

[3]  James P. Cohoon,et al.  A Spiffy tool for the simultaneous placement and global routing for three-dimensional field-programmable gate arrays , 1999, Proceedings Ninth Great Lakes Symposium on VLSI.

[4]  James P. Cohoon,et al.  A Parallel VLSI Circuit Layout Methodology , 1993, The Sixth International Conference on VLSI Design.

[5]  Allen C.-H. Wu Yuh-Sheng Lee.  A Performance and Routability Driven Router for FPGAs Considering Path Delays , 1995, DAC 1995.

[6]  Miriam Leeser,et al.  Rothko: A three dimensional FPGA architecture, its fabrication, and design tools , 1997, FPL.

[7]  Y. Kajitani,et al.  The channeled-BSG: a universal floorplan for simultaneous place/route with IC applications , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[8]  Rob A. Rutenbar,et al.  Performance-driven simultaneous placement and routing for FPGA's , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Vaughn Betz,et al.  VPR: A new packing, placement and routing tool for FPGA research , 1997, FPL.

[10]  Jonathan Rose.  Parallel global routing for standard cells , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Daniel Brélaz,et al.  New methods to color the vertices of a graph , 1979, CACM.

[12]  Malgorzata Marek-Sadowska,et al.  Orthogonal Greedy Coupling - A New Optimization Approach to 2-D FPGA Routing , 1995, 32nd Design Automation Conference.

[13]  Alfred V. Aho,et al.  Compilers: Principles, Techniques, and Tools , 1986, Addison-Wesley series in computer science / World student series edition.

[14]  Allen C.-H. Wu,et al.  A Performance and Routability Driven Router for FPGAs Considering Path Delays , 1995, 32nd Design Automation Conference.