Modeling, simulation and performance evaluation for a CIOQ switch architecture

The intense growth experienced by the Internet on the past decade has motivated a considerable development in packet switching architectures. Several architectures have been proposed and implemented. Combined input-output queuing (CIOQ) is one of such successful architectures. In this paper, we present a proposal of modeling, simulation and performance evaluation for two CIOQ switch architectures developed by Santos and Motoyama. The main objective is to evaluate their performance and to compare main results. The performance evaluation covers blocking probability, mean and maximum queuing occupation for several switch dimensions and load intensities. Finally, we validated the proposal models and proved that Santos and Motoyama architectures are very efficient, with small blocking probabilities and queuing requirements.

[1]  Jean C. Walrand,et al.  Achieving 100% throughput in an input-queued switch , 1996, Proceedings of IEEE INFOCOM '96. Conference on Computer Communications.

[2]  Carlos Roberto dos Santos,et al.  A QoS Provisioned CIOQ ATM Switch with m Internal Links , 2004, ICT.

[3]  Yuval Tamir,et al.  High-performance multiqueue buffers for VLSI communication switches , 1988, [1988] The 15th Annual International Symposium on Computer Architecture. Conference Proceedings.

[4]  C. Minkenberg,et al.  A combined input and output queued packet switched system based on PRIZMA switch on a chip technology , 2000, IEEE Communications Magazine.

[5]  Thomas G. Robertazzi,et al.  Input Versus Output Queueing on a SpaceDivision Packet Switch , 1993 .

[6]  Riccardo Melen.  Reviews and New Releases Achille Pattavina. Switching Theory, Architectures and Performance in Broadband atm Networks John Wiley & Sons, 1998 , 1999 .

[7]  Ken Christensen,et al.  An evolution to crossbar switches with virtual output queuing and buffered cross points , 2003 .

[8]  Achille Pattavina,et al.  Switching theory : architectures and performance in broadband ATM networks , 1998 .

[9]  Jun Wu,et al.  DRR A Fast High-Throughput Scheduling Algorithm for Combined Input Crosspoint-Queued CICQ Switches , 2005, 13th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems.

[10]  Marco Ajmone Marsan,et al.  On the stability of input-queued switches with speed-up , 2001, TNET.

[11]  Samuel P. Morgan,et al.  Input Versus Output Queueing on a Space-Division Packet Switch , 1987, IEEE Trans. Commun..

[12]  Y. Tamir,et al.  High-performance multi-queue buffers for VLSI communications switches , 1988, ISCA '88.

[13]  Nick McKeown,et al.  Matching output queueing with a combined input output queued switch , 1999, IEEE INFOCOM '99. Conference on Computer Communications. Proceedings. Eighteenth Annual Joint Conference of the IEEE Computer and Communications Societies. The Future is Now (Cat. No.99CH36320).