Automatic Layer-Based Generation of System-On-Chip Bus Communication Models

With growing market pressures and rising system complexities, automated system-level communication design with efficient design space exploration capabilities is becoming increasingly important. At the same time, customized network-oriented communication architectures become necessary in enabling a high-performance communication among the system components. To this end, corresponding communication design flows that are supported by efficient design automation techniques need to be developed. In this paper, we present a system-level design environment for the generation of bus-based system-on-chip architectures. Our approach supports a two-stage design flow using automated model refinement toward custom heterogeneous communication networks. Starting from an abstract specification of the desired communication channels, our environment automatically generates tailored network models at various levels of abstraction. At its core, an automatic layer-based refinement approach is utilized. We have applied our approach to a set of industrial-strength examples with a wide range of target architectures. Our experimental results show significant productivity gains over a traditional communication design, allowing early and rapid design space exploration.

[1]  Manfred Glesner,et al.  Bus-Based Communication Synthesis on System-Level , 1996, TODE.

[2]  Hugo De Man,et al.  CoWare—A design environment for heterogeneous hardware/software systems , 1996, EURO-DAC '96/EURO-VHDL '96.

[3]  Gabriela Nicolescu,et al.  Multiprocessor SoC platforms: a component-based design approach , 2002, IEEE Design & Test of Computers.

[4]  Andreas Gerstlauer,et al.  RTOS modeling for system level design , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[5]  Wayne H. Wolf,et al.  Communication synthesis for distributed embedded systems , 1995, ICCAD.

[6]  Srinivasan Murali,et al.  SUNMAP: a tool for automatic topology selection and generation for NoCs , 2004, Proceedings. 41st Design Automation Conference, 2004..

[7]  Radu Marculescu,et al.  Energy- and performance-aware mapping for regular NoC architectures , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Patrick Schaumont,et al.  Techniques to evolve a C++ based system design language , 2002, Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition.

[9]  Andreas Gerstlauer,et al.  Automatic network generation for system-on-chip communication design , 2005, 2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05).

[10]  Amer Baghdadi,et al.  Automatic generation of application-specific architectures for heterogeneous multiprocessor system-on-chip , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[11]  Daniel D. Gajski,et al.  System-On-Chip Component Models , 2003 .

[12]  Sujit Dey,et al.  Efficient exploration of the SoC communication architecture design space , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[13]  Radu Marculescu,et al.  Energy- and performance-driven NoC communication architecture synthesis using a decomposition approach , 2005, Design, Automation and Test in Europe.

[14]  Miltos D. Grammatikakis,et al.  IPSIM: systemc 3.0 enhancements for communication refinement , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[15]  Luciano Lavagno,et al.  Scalable techniques for system-level cosimulation and coestimation , 2003 .

[16]  Andreas Gerstlauer,et al.  Necessary and Sufficient Functionality and Parameters for SoC Communication , 2006 .

[17]  Gabriela Nicolescu,et al.  Component-based design approach for multicore SoCs , 2002, DAC '02.

[18]  Krishnan Srinivasan,et al.  Linear programming based techniques for synthesis of network-on-chip architectures , 2006, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

[19]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[20]  A. Gerstlauer,et al.  System-level communication modeling for network-on-chip synthesis , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[21]  Manfred Glesner,et al.  Generation of interconnect topologies for communication synthesis , 1998, Proceedings Design, Automation and Test in Europe.

[22]  Sharad Malik,et al.  A hierarchical modeling framework for on-chip communication architectures , 2002, ICCAD 2002.

[23]  Daniel Gajski,et al.  Embedded software generation from system level design languages , 2004, ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753).

[24]  Gunar Schirner,et al.  Quantitative Analysis of Transaction Level Models for the AMBA Bus , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[25]  Dietmar Müller,et al.  SystemC/sup SV/: an extension of SystemC for mixed multi-level communication modeling and interface-based system design , 2001, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001.

[26]  Alberto L. Sangiovanni-Vincentelli,et al.  Addressing the system-on-a-chip interconnect woes through communication-based design , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[27]  Andreas Gerstlauer,et al.  Automatic Generation of Communication Architectures , 2005, IESS.

[28]  Diederik Verkest,et al.  Hardware/software co-design of digital telecommunication systems , 1997, Proc. IEEE.

[29]  Ieee Circuits,et al.  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems information for authors , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[30]  Daniel D. Gajski,et al.  C-based Interactive RTL Design Methodology , 2004 .

[31]  Robert Günzel,et al.  TRAIN: A Virtual Transaction Layer Architecture for TLM-based HW/SW Codesign of Synthesizable MPSoC , 2006, Proceedings of the Design Automation & Test in Europe Conference.