Garp: a MIPS processor with a reconfigurable coprocessor

Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications.

[1]  Robert Ulichney,et al.  Digital Halftoning , 1987 .

[2]  Daniel P. Lopresti,et al.  Building and using a highly parallel programmable logic array , 1991, Computer.

[3]  Harvey F. Silverman,et al.  Processor reconfiguration through instruction-set metamorphosis , 1993, Computer.

[4]  Bruce Schneier,et al.  Applied cryptography : protocols, algorithms, and source codein C , 1996 .

[5]  Michael D. Smith,et al.  A high-performance microarchitecture with hardware-programmable functional units , 1994, Proceedings of MICRO-27. The 27th Annual IEEE/ACM International Symposium on Microarchitecture.

[6]  André DeHon,et al.  DPGA-coupled microprocessors: commodity ICs for the early 21st Century , 1994, Proceedings of IEEE Workshop on FPGA's for Custom Computing Machines.

[7]  Eric Lemoine,et al.  Run time reconfiguration of FPGA for scanning genomic databases , 1995, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[8]  Brad L. Hutchings,et al.  A dynamic instruction set computer , 1995, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[9]  Ralph Wittig,et al.  OneChip: an FPGA processor with reconfigurable logic , 1996, 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[10]  Bernard K. Gunther,et al.  Assessing document relevance with run-time reconfigurable machines , 1996, 1996 Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[11]  André DeHon,et al.  Reconfigurable architectures for general-purpose computing , 1996 .

[12]  Mark Shand,et al.  Programmable active memories: reconfigurable systems come of age , 1996, IEEE Trans. Very Large Scale Integr. Syst..