Improving the Third Quadrant Operation of Superjunction MOSFETs by Using the Cascode Configuration

In this paper, the third quadrant behavior of a high-voltage superjunction <sc>mosfet</sc> (SJ-FET) in cascode configuration (CC) with a low-voltage silicon <sc>mosfet</sc> is deeply studied by means of an analytical model and experimental data. The third quadrant dynamic behavior of the SJ-CCs is compared to the standalone counterparts by evaluating their reverse recovery time (t<sub>RR</sub>), reverse recovery peak current (I<sub>RRM</sub>), and reverse recovery charge (Q<sub>RR</sub>). An analytical model and experimental results show that the SJ-CC avoids or mitigates the activation of the SJ-FET body diode during the third quadrant operation. As a consequence, the SJ-CC strongly improves the widely used figure-of-merit R<sub>ON</sub>·Q<sub>RR</sub>, which considers the <sc>on</sc>-state resistance of the transistors (R<sub>ON</sub>). In addition, the results obtained using an SJ-CC are similar or better than those achieved by SJ-FETs with enhanced reverse recovery (i.e., irradiated SJ-FETs). This paper also includes a comparison with commercial wide bandgap switches, concluding that the R<sub>ON</sub>·Q<sub>RR</sub> value provided by the SJ-CC is around eight times higher than that provided by a commercial GaN cascode.

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