A physical model for gate-to-body tunneling current and its effects on floating-body PD/SOI CMOS devices and circuits

Abstract Direct gate-to-body tunneling current, which can possibly drive, and/or ameliorate floating-body effects in PD/SOI MOSFETs, is physically modeled and examined. Predominant valence-band and conduction-band carrier tunneling components are modeled for inversion, depletion, and accumulation conditions by modifying the classical independent-electron formalism. Several important scaled-device effects, which have been overlooked in contemporary modeling of gate tunneling current, are identified and accounted for. The model shows good agreement with measured data for gate-oxide thickness varying down to 1.65 nm. Use of the model in device and circuit simulations suggests that the gate-to-body tunneling current can be beneficial in controlling dynamic floating-body effects in particular applications. However, the significance of the benefits is diminished for scaled PD/SOI CMOS when the supply voltage is reduced and when the technology is, necessarily, optimized to suppress the detrimental DC floating-body effects on off-state current.

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