A digitally programmable delay chip with picosecond resolution

A digitally programmable delay chip fabricated on MOSAIC III, an advanced bipolar process, is described. The CML/ECL-based design comprises a digitally programmable delay chain and an analog vernier adjustment to achieve high-resolution capability. The architecture and fabrication process are described. Results from a test vehicle have demonstrated an average coarse step size of 110 ps and a fine tune resolution of 0.5 ps. A production version with improved linearity and reduced delay variation with temperature has been developed.<<ETX>>