Area–Oriented Technology Mapping for LUT–Based Logic Blocks

Abstract One of the main aspects of logic synthesis dedicated to FPGA is the problem of technology mapping, which is directly associated with the logic decomposition technique. This paper focuses on using configurable properties of CLBs in the process of logic decomposition and technology mapping. A novel theory and a set of efficient techniques for logic decomposition based on a BDD are proposed. The paper shows that logic optimization can be efficiently carried out by using multiple decomposition. The essence of the proposed synthesis method is multiple cutting of a BDD. A new diagram form called an SMTBDD is proposed. Moreover, techniques that allow finding the best technology mapping oriented to configurability of CLBs are presented. In the experimental section, the presented method (MultiDec) is compared with academic and commercial tools. The experimental results show that the proposed technology mapping strategy leads to good results in terms of the number of CLBs.

[1]  C. Scholl,et al.  The multiple variable order problem for binary decision diagrams: theory and practical application , 2001, Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455).

[2]  Jan Schmidt,et al.  The Case for a Balanced Decomposition Process , 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.

[3]  Dariusz Kania,et al.  SMTBDD: New Concept of Graph for Function Decomposition , 2015 .

[4]  Qiang Wang,et al.  Area-efficient FPGA logic elements: Architecture and synthesis , 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

[5]  Petr Mikusek.  Multi-terminal BDD synthesis and applications , 2009, 2009 International Conference on Field Programmable Logic and Applications.

[6]  Giovanni De Micheli,et al.  Synthesis and Optimization of Digital Circuits , 1994 .

[7]  Adam Opara,et al.  Decomposition-based logic synthesis for PAL-based CPLDs , 2010, Int. J. Appl. Math. Comput. Sci..

[8]  Maciej J. Ciesielski,et al.  BDS: a BDD-based logic optimization system , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Christoph Scholl.  Functional decomposition with applications to FPGA synthesis , 2001 .

[10]  Wai-Kei Mak,et al.  ALMmap: Technology Mapping for FPGAs With Adaptive Logic Modules , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  Yu-Liang Wu,et al.  Further Improve Excellent Graph-Based FPGA Technology Mapping by Rewiring , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[12]  Tsutomu Sasao,et al.  A method to represent multiple-output switching functions by using multi-valued decision diagrams , 1996, Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96).

[13]  Hiroyuki Ochi,et al.  Breadth-first manipulation of SBDD of boolean functions for vector processing , 1991, 28th ACM/IEEE Design Automation Conference.

[14]  M. Ciesielski,et al.  BDS: a BDD-based logic optimization system , 2000, Proceedings 37th Design Automation Conference.

[15]  K. Karplus,et al.  Xtmap: generate-and-test mapper for table-lookup gate arrays , 1993, Digest of Papers. Compcon Spring.

[16]  Sheldon B. Akers,et al.  Binary Decision Diagrams , 1978, IEEE Transactions on Computers.

[17]  On Using Permutation of Variables to Improve the Iterative Power of Resynthesis Petr Fiser , 2012 .

[18]  Gabriele Saucier,et al.  Input-driven partitioning methods and application to synthesis on table-lookup-based FPGAs , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[19]  Massoud Pedram,et al.  OBDD-based function decomposition: algorithms and implementation , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[20]  Russell Tessier,et al.  BDD-based logic synthesis for LUT-based FPGAs , 2002, TODE.

[21]  Sofia Cassel,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 2012 .

[22]  Rajeev Murgai,et al.  Improved logic synthesis algorithms for table look up architectures , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[23]  Jason Cong,et al.  DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs , 2004, ICCAD 2004.

[24]  Jonathan Rose,et al.  Chortle: a technology mapping program for lookup table-based field programmable gate arrays , 1990, 27th ACM/IEEE Design Automation Conference.

[25]  Mariusz Rawski,et al.  Non-disjoint decomposition of Boolean functions and its application in FPGA-oriented technology mapping , 1997, EUROMICRO 97. Proceedings of the 23rd EUROMICRO Conference: New Frontiers of Information Technology (Cat. No.97TB100167).

[26]  H. A. Curtis,et al.  A new approach to The design of switching circuits , 1962 .

[27]  Jason Cong,et al.  FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[28]  Qiang Wang,et al.  Raising FPGA Logic Density Through Synthesis-Inspired Architecture , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[29]  Martin D. F. Wong,et al.  DDBDD: Delay-Driven BDD Synthesis for FPGAs , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[30]  Sze-Tsen Hu.  ON THE DECOMPOSITION OF SWITCHING FUNCTIONS , 1961 .

[31]  Václav Dvorák,et al.  Heuristic Synthesis of Multi-Terminal BDDs Based on Local Width/Cost Minimization , 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.

[32]  Robert K. Brayton,et al.  ABC: An Academic Industrial-Strength Verification Tool , 2010, CAV.

[33]  Shih-Chieh Chang,et al.  Technology Mapping via Transformations of Function Graphs , 1992, ICCD.

[34]  Tsutomu Sasao,et al.  Shared Multi-Terminal Binary Decision Diagrams for Multiple-Output Functions (Special Section on VLSI Design and CAD Algorithms) , 1998 .

[35]  Bernard Wyrwol,et al.  Decomposition of the fuzzy inference system for implementation in the FPGA structure , 2013, Int. J. Appl. Math. Comput. Sci..

[36]  Marcin Kubica,et al.  Decomposition of multi-output functions oriented to configurability of logic blocks , 2017 .

[37]  Robert K. Brayton,et al.  Mapping into LUT structures , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[38]  D. E. Long,et al.  The design of a cache-friendly BDD library , 1998, 1998 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (IEEE Cat. No.98CB36287).

[39]  Hamid R. Zarandi,et al.  A New CLB Architecture for Tolerating SEU in SRAM-Based FPGAs , 2009, 2009 International Conference on Reconfigurable Computing and FPGAs.

[40]  Yuan Wang,et al.  A new configurable logic block with 4/5-input configurable LUT and fast/slow-path carry chain , 2011, 2011 9th IEEE International Conference on ASIC.

[41]  Wei Wan,et al.  A new approach to the decomposition of incompletely specified multi-output functions based on graph coloring and local transformations and its application to FPGA mapping , 1992, Proceedings EURO-DAC '92: European Design Automation Conference.

[42]  V. Kamakoti,et al.  A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs , 2005, ASP-DAC.

[43]  Jason Cong,et al.  Optimality Study of Logic Synthesis for LUT-Based FPGAs , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[44]  Jing-Yang Jou,et al.  ALTO: an iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping , 2000, IEEE Trans. Very Large Scale Integr. Syst..

[45]  Rolf Drechsler,et al.  SBDD variable reordering based on probabilistic and evolutionary algorithms , 1999, 1999 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM 1999). Conference Proceedings (Cat. No.99CH36368).