In this paper, Silex Microsystems, the world's largest Pure-Play MEMS foundry, together with partners TNO and VTT, present our recent advancements in RF through silicon Vias (TSV) for 3D integrated passive devices (IPD) applications, achieved in conjunction with the European consortium EPAMO. A novel open TSV fabrication process on 200 mm diameter 305 μm thick High Resistivity wafers has been used to demonstrated High Aspect Ratio Through Silicon Vias (HAR TSV), focusing on tight pitch, resulting in 36 TSV/mm2 Via density. 305 μm wafer thickness enables the fabrication of rigid interposers, an advancement in the commercialization of 3D packaging technology. The fabrication includes double sided deep reactive ion etching (DRIE), developments and evaluation on various conformal high aspect ratio (HAR) plating seedlayer processes, and void-free TSV Cu plating of open rigid TSV structures and bonding to glass wafers for characterization. The electrical characterization of the fabricated devices was performed by VTT with excellent measured RF properties: in specific, low RF losses as well as low DC resistances of less than 20 mOhm/TSV. Several different coplanar waveguide (CPW) test vehicles and other RF TSV test structures together with Daisy Chain and parasitic Capacitance test structures were designed, fabricated and evaluated. The loss of a single coplanar TSV transition is less than 0.04 dB @ 5 GHz, which is considered to be very small. The developed TSV technology was also employed to fabricate 3D toroidal inductors. These inductors were characterized by TNO showing high Q-factor (>30) and self-resonance frequency (> 6 GHz) for 3D inductors in the range of 1-15 nH. 1 and 2 port inductor temperature characteristics over temperature interval from room temperature to 111°C are reported. A fabrication integration scheme for fully integrated RF-IPD with 3D TSV based inductors and high ohmic polysilicon (p-Si) resistors and piezoelectric (PZT) metal-insulator-metal (MIM) capacitors are discussed. Outlook for improvements using integrated high frequency magnetic flux materials and commercialization aspects are described.
[1]
V. N. Sekhar,et al.
Low-Loss Broadband Package Platform With Surface Passivation and TSV for Wafer-Level Packaging of RF-MEMS Devices
,
2013,
IEEE Transactions on Components, Packaging and Manufacturing Technology.
[2]
S. Wong,et al.
Ultra-Low Resistance, Through-Wafer Via (TWV) Technology and Its Applications in Three Dimensional Structures on Silicon
,
1998
.
[3]
M. Pardoen,et al.
Reducing the substrate losses of RF integrated inductors
,
1998
.
[4]
Thorbjörn Ebefors,et al.
RECENT RESULTS USING MET-VIA TSV INTERPOSER TECHNOLOGY AS TMV ELEMENT IN WAFER LEVEL THROUGH MOLD VIA PACKAGING OF CMOS BIOSENSORS
,
2013
.
[5]
C. Cané,et al.
Improvement of the quality factor of RF integrated inductors by layout optimization
,
1998,
1998 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium. Digest of Papers (Cat. No.98CH36182).
[6]
L.P.B. Katehi,et al.
High-Q integrated 3-D inductors and transformers for high frequency applications
,
2004,
2004 IEEE MTT-S International Microwave Symposium Digest (IEEE Cat. No.04CH37535).
[7]
Xiaoyu Mi,et al.
Integrated Passives for High-Frequency Applications
,
2010
.