Split-channel antifuse array architecture

In general, the present invention provides a gate oxide antifuse transistor device of varying thickness that can be employed in nonvolatile, one-time programmable memory (OTP) array applications. Antifuse transistors can be fabricated in standard CMOS technology and consist of standard transistor elements with source diffusion, gate oxidation, polysilicon gate and light drain diffusion. Just below polysilicon, various gate oxidations consist of thick gate oxide regions and thin gate oxide regions, which act as localized breakdown voltage zones. The conductive channel between the polysilicon gate and the channel region may be formed in the breakdown voltage zone during the programming operation. In memory array applications, a wordline applied to a polysilicon gate may be sensed through a bitline connected to source diffusion via a word fuse anti-fuse transistor channel. More specifically, the present invention provides an effective method for using a separate channel MOS structure as an antifuse cell suitable for OTP memory.