3D scheduling: high-level synthesis with floorplanning

Submicron feature sizes result in designs in which wiring delay is comparable to functional delay. This paper presents a new approach to the problem of scheduling while simultaneously considering floorplanning. Operators are assigned (and placed) as close as possible to their predecessors in order to minimize the interconnection cost. We also propose an algorithm to reduce interconnection cost by introducing redundant operators. This procedure produces a quite satisfactory result for a practical size example, especially on critical-path dominated cases.