A Reconfigurable Multicomputer System for Robotics Applications

Architecture of a reconfigurable cache-based multicomputer system for intelligent machines/robotics applications is discussed. To overcome the memory access latency and conflicts, extensive cacheing of instructions and data is performed in each processor node. This architecture utilizes distributed common memory, multiported RAM, and private cache storage between the local distributed common memory and the local processor. A simple interface circuit which permits multiple microprocessors to share a common memory is described. Theoretical model for task execution time, for the multiprocessor system is presented.

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