Lock and Fence When Needed: State Space Exploration + Static Analysis = Improved Fence and Lock Insertion

[1]  Daniel Kroening,et al.  SAT-Based Model Checking , 2018, Handbook of Model Checking.

[2]  David A. Padua,et al.  Compiler techniques for high performance sequentially consistent java programs , 2005, PPOPP.

[3]  Dragan Bosnacki,et al.  GPUexplore: Many-Core On-the-Fly State Space Exploration Using GPUs , 2014, TACAS.

[4]  Jens Palsberg,et al.  A formalization of Java’s concurrent access modes , 2019, Proc. ACM Program. Lang..

[5]  Jan Friso Groote,et al.  Solving Parameterised Boolean Equation Systems with Infinite Data Through Quotienting , 2018, FACS.

[6]  Eran Yahav,et al.  Partial-coherence abstractions for relaxed memory models , 2011, PLDI '11.

[7]  Lubos Brim,et al.  DiVinE 3.0 - An Explicit-State Model Checker for Multithreaded C & C++ Programs , 2013, CAV.

[8]  Sarita V. Adve,et al.  Shared Memory Consistency Models: A Tutorial , 1996, Computer.

[9]  Leslie Lamport,et al.  How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs , 2016, IEEE Transactions on Computers.

[10]  Parosh Aziz Abdulla,et al.  The Best of Both Worlds: Trading Efficiency and Optimality in Fence Insertion for TSO , 2015, ESOP.

[11]  Jade Alglave,et al.  Fences in Weak Memory Models , 2010, CAV.

[12]  Robert Colvin,et al.  A wide-spectrum language for verification of programs on weak memory models , 2018, FM.

[13]  Bengt Jonsson.  State-space exploration for concurrent algorithms under weak memory orderings: (preliminary version) , 2009, CARN.

[14]  Anton Wijs,et al.  REFINER: Towards Formal Verification of Model Transformations , 2014, NASA Formal Methods.

[15]  Shaked Flur,et al.  Simplifying ARM concurrency: multicopy-atomic axiomatic and operational models for ARMv8 , 2017, Proc. ACM Program. Lang..

[16]  Roland Meyer,et al.  Checking and Enforcing Robustness against TSO , 2013, ESOP.

[17]  Jeehoon Kang,et al.  Repairing sequential consistency in C/C++11 , 2017, PLDI.

[18]  Jade Alglave,et al.  Stability in Weak Memory Models , 2011, CAV.

[19]  David L Weaver,et al.  The SPARC architecture manual : version 9 , 1994 .

[20]  Jaejin Lee,et al.  Hiding relaxed memory consistency with a compiler , 2001 .

[21]  Erik P. de Vink,et al.  The mCRL2 Toolset for Analysing Concurrent Systems - Improvements in Expressivity and Usability , 2019, TACAS.

[22]  Sebastian Burckhardt,et al.  Effective Program Verification for Relaxed Memory Models , 2008, CAV.

[23]  Yuanyuan Zhou,et al.  Learning from mistakes: a comprehensive study on real world concurrency bug characteristics , 2008, ASPLOS.

[24]  John Wickerson,et al.  Overhauling SC atomics in C11 and OpenCL , 2016, POPL.

[25]  Gerard J. Holzmann,et al.  The SPIN Model Checker - primer and reference manual , 2003 .

[26]  Radek Pelánek,et al.  BEEM: Benchmarks for Explicit Model Checkers , 2007, SPIN.

[27]  Yun Zhang,et al.  Static data race detection for concurrent programs with asynchronous calls , 2009, ESEC/FSE '09.

[28]  Peter Sewell,et al.  A Better x86 Memory Model: x86-TSO , 2009, TPHOLs.

[29]  Mohamed Faouzi Atig,et al.  Getting Rid of Store-Buffers in TSO Analysis , 2011, CAV.

[30]  Dennis Shasha,et al.  Efficient and correct execution of parallel programs that share memory , 1988, TOPL.

[31]  Daniel Kroening,et al.  Don’t Sit on the Fence , 2013, ACM Trans. Program. Lang. Syst..

[32]  Dragan Bosnacki,et al.  GPUexplore 2.0: Unleashing GPU Explicit-State Model Checking , 2016, FM.

[33]  Feng Liu,et al.  Dynamic synthesis for relaxed memory models , 2012, PLDI.

[34]  Jaejin Lee,et al.  Automatic fence insertion for shared memory multiprocessing , 2003, ICS '03.

[35]  Pierre Wolper,et al.  A Verification-Based Approach to Memory Fence Insertion in PSO Memory Systems , 2013, TACAS.

[36]  Cees T. A. M. de Laat,et al.  A Medium-Scale Distributed System for Computer Science Research: Infrastructure for the Long Term , 2016, Computer.

[37]  Sagar Chaki,et al.  BDD-Based Symbolic Model Checking , 2018, Handbook of Model Checking.

[38]  Ali Sezgin,et al.  Modelling the ARMv8 architecture, operationally: concurrency and ISA , 2016, POPL.

[39]  Nir Shavit,et al.  Software transactional memory , 1995, PODC '95.

[40]  Robert E. Tarjan,et al.  Enumeration of the Elementary Circuits of a Directed Graph , 1972, SIAM J. Comput..

[41]  Parosh Aziz Abdulla,et al.  Memorax, a Precise and Sound Tool for Automatic Fence Insertion under TSO , 2013, TACAS.