Conformance of ECD wafer bumping to future demands on CSP, 3D integration, and MEMS

A bumping technique which is based on electrochemical deposition (ECD) of various metals and metal alloys on wafer level will be presented and characterized in this paper. The machining of the single process steps principally origins from front-end technology widely using standard equipment, but mainly differing in structure sizes and layer thicknesses. Photosensitive polymers have been coated to repassivate the IC wafer and to serve as dielectric layers for I/O redistribution. Sputtering of the under-bump metallization (UBM), lithographical printing of resist pattern, electroplating of the bump metal, and selective etching of the plating base will be treated in detail. Different kinds of UBMs are used for the various bump metals. A sputtered Ti:W(N)/Au thin-film layer is used for the electroplating of Au and Au/Sn, and a Ti:W/Cu metallization acts as the seed layer for Cu and Ni/Au deposition as well as for the solder (SnPb37, PbSn5, SnAg3.5, SnCu0.7). Alternatively, other UBMs such as Ti/Ti:Ni/Ni, Ti/Au, and Cr/Cr:Cu/Cu has been qualified to generate several reliable solder bump metallurgies. Both spin-coating and spray-coating are used as a method to deposit the liquid photoresist onto the wafer. By applying a highly viscous system, layer thicknesses from 5 mum up to 90 mum with excellent thickness homogeneity and a precise pattern resolution for all standard wafer sizes can be achieved. A high standard of bump geometry as well as a high process quality and long term reliability can be obtained by carefully chosen electrolytes, well defined plating conditions, and specially developed microgalvanic equipment. Adequate wet etching solutions had to be formulated to get a neglectable corrosion affect on the bump surface and a minimum bump undercut. Thermal, mechanical, and electrical tests were performed to get statements about the reliability of the bumped devices