Behavioral synthesis of high performance, low cost, and low power application specific processors for linear computations

Throughput has been widely traditionally recognized as the most popular performance metric for implementation of application specific computations. However, increasingly applications such as embedded controllers impose constraints on both throughput and latency as important metrics of speed. Although throughput alone can be arbitrarily improved for several classes of systems using previously published techniques, none of those approaches are effective when latency constraints are considered. DSP, communications, and control systems are often either linear, or have subsystems that are linear. Recently an optimal technique for simultaneous optimization of throughput and latency of linear computations was introduced by M.B. Srivastava and M. Potkonjak (1994). However, in many cases this technique introduces significant area overhead. We apply certain key aspects of that technique (on-arrival-processing and maximally fast implementation of linear computations) with exploration of state-space based transformations to develop four synthesis techniques which generate high throughput, low latency, low area, and low power application specific processors for the special case of single input linear computations. The new transformation techniques can also be used to increase the implementation efficiency while achieving the same latency and throughput as the original design-we obtained large improvements in area and power on many benchmarks when using the proposed transformations in this alternate role.<<ETX>>