The Need For Formal Verification In Hardware Design And What Formal Verification Has Not Done For Me Lately

The problem of verifying that the design of an integrated circuit will perform the tasks required by its specification is currently a perplexing one for circuit designers. Unfortunately, formal verification techniques in general, and theorem proving techniques in particular, have not been able to alleviate this problem. This paper briefly outlines the verification tasks required in a circuit design and identify those verification tasks for which formal approaches may be most beneficial.

[1]  Steven D. Johnson,et al.  A Tactical Framework for Hardware Design , 1988 .

[2]  Kurt Keutzer,et al.  Synthesis of robust delay-fault-testable circuits: practice , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Kurt Keutzer,et al.  Design verification and reachability analysis using algebraic manipulation , 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[4]  Eduard Cerny,et al.  Comparing Generic State Machines , 1991, CAV.

[5]  David L. Dill,et al.  Formal verification of cache systems using refinement relations , 1990, Proceedings., 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[6]  John McCarthy,et al.  Mathematical Theory of Computation , 1991 .

[7]  John M. Rushby,et al.  Design Choices In Specification Languages And Verification Systems , 1991, 1991., International Workshop on the HOL Theorem Proving System and Its Applications.

[8]  Orna Grumberg,et al.  Research on Automatic Verification of Finite-State Concurrent Systems , 1987 .

[9]  Jeffrey J. Joyce,et al.  Formal Verification and Implementation of a Microprocessor , 1988 .

[10]  Wojciech Maly,et al.  Realistic Fault Modeling for VLSI Testing , 1987, 24th ACM/IEEE Design Automation Conference.

[11]  Edmund M. Clarke,et al.  Sequential circuit verification using symbolic model checking , 1991, DAC '90.