Design of a high gain and highly linear common-gate UWB mixer in K-band

In this paper, in order to design a K-band common-gate Gilbert-cell mixer via a 0.18 μm CMOS technology, the π-Network and post-distortion cancellation (PDC) techniques are implemented simultaneously, resulting in the improvement of gain, bandwidth, noise figure and linearity. Also, a new method for implementing the π-Network, using the parasitic capacitances between RF and LO stage nodes, is proposed which improves the mixer performance and makes the mixer design possible at high frequencies. It is shown that the π-Network enhances the gain and bandwidth by generating complex poles in system frequency response without the need for extra power consumption. The suitable location of these poles, which gives rise to high gain and high bandwidth, is discussed and determined by MATLAB simulation. Results of simulation illustrate 3.36 dB improvement in power conversion gain and 2 dB reduction in noise figure at the same power consumption with LO power of −1 dBm in comparison with the case when PDC technique is used only. Compared to conventional mixer, it improves the IIP3 by 6 dB. Also, the power consumption of the mixer together with the designed bias circuit is 9.68 mW at 1.8 V.