Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis
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[1] Kazutoshi Kobayashi,et al. Measurement results of within-die variations on a 90nm LUT array for speed and yield enhancement of reconfigurable devices , 2006, Asia and South Pacific Conference on Design Automation, 2006..
[2] Charles E. Stroud,et al. BIST-Based Delay-Fault Testing in FPGAs , 2003, J. Electron. Test..
[3] Chandu Visweswariah,et al. Death, taxes and failing chips , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).
[4] Yan Lin,et al. FPGA device and architecture evaluation considering process variations , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..
[5] Premachandran R. Menon,et al. BIST-based delay path testing in FPGA architectures , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).
[6] A. Asenov,et al. Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness , 2003 .
[7] Subhasish Mitra,et al. Delay defect characteristics and testing strategies , 2003, IEEE Design & Test of Computers.
[8] K. Ravindran,et al. First-Order Incremental Block-Based Statistical Timing Analysis , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[9] Sani R. Nassif. Design for Variability in DSM Technologies , 2000 .
[10] Yan Lin,et al. Placement and Timing for FPGAs Considering Variations , 2006, 2006 International Conference on Field Programmable Logic and Applications.
[11] Farid N. Najm,et al. An adaptive FPGA architecture with process variation compensation and reduced leakage , 2006, 2006 43rd ACM/IEEE Design Automation Conference.
[12] Peter Y. K. Cheung,et al. Within-die delay variability in 90nm FPGAs and beyond , 2006, 2006 IEEE International Conference on Field Programmable Technology.
[13] Tobias Becker,et al. Modular dynamic reconfiguration in Virtex FPGAs , 2006 .
[14] Kazutoshi Kobayashi,et al. A yield and speed enhancement scheme under within-die variations on 90nm LUT array , 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..
[15] A. Asenov,et al. Intrinsic threshold voltage fluctuations in decanano MOSFETs due to local oxide thickness variations , 2002 .
[16] Puneet Gupta,et al. Design sensitivities to variability: extrapolations and assessments in nanometer VLSI , 2002, 15th Annual IEEE International ASIC/SOC Conference.
[17] Xiao-Yu Li,et al. FPGA as Process Monitor-an effective method to characterize poly gate CD variation and its impact on product performance and yield , 2004, IEEE Transactions on Semiconductor Manufacturing.
[18] Vladimir Zolotov,et al. Parameterized block-based statistical timing analysis with non-Gaussian parameters, nonlinear delay functions , 2005, Proceedings. 42nd Design Automation Conference, 2005..
[19] Andrzej Krasniewski. Evaluation of Testability of Path Delay Faults for User-Configured Programmable Devices , 2003, FPL.
[20] Patrick Girard,et al. High quality TPG for delay faults in look-up tables of FPGAs , 2004, Proceedings. DELTA 2004. Second IEEE International Workshop on Electronic Design, Test and Applications.