Resistive switching behavior of a CeO2 based ReRAM cell incorporated with Si buffer layer

Abstract We propose a novel resistive switching device with a W/CeO 2 /Si/TiN structure by incorporating a very thin Si buffer layer in the interface, the memory performance of this device such as forming voltage, operation power, and window and endurance characteristics were found to be remarkably improved compared with the performance of the device without the Si layer. This improvement was attributed to the formation of Ce-silicate and thus proper introduction of oxygen vacancies at the interface. The gradual reset process of the W/CeO 2 /Si/TiN device under sweeping voltage was quantitatively analyzed by parallel conductive filaments model. Our results provide a guideline for the operation voltage control for further optimizing device performance and give new insights into the gradual reset process.

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