DfT-based External Test and Diagnosis of Mesh-like Networks on Chips. Testitavusel põhinev välise testi ja diagnoosi meetod kahemõõtmelistele kiipvõrkudele

Future integrated systems will contain billions of transistors, composing tens to hundred of IP cores which are capable of delivering rich multimedia and networking services. As the number of devices in the integrated circuit increases, the limitations of traditional bus architectures are exposed. Networks on Chips (NoC) have emerged as the new backbone for chip integration. Due to their particular topology on one hand, and their scale on the other hand, it is crucial to develop a methodology that could handle testing of such new kind of architectures. In this thesis we discuss an external test method which achieves high fault coverage. In addition to that the test method is scalable, and has a low overhead area. Secondly we propose the use of the functional test configurations with a goal to locate faults in individual links of the switches. Collapsing of link faults based on equivalent configurations was also proposed. Using this, a method was proposed that is capable of unambiguously diagnose a link fault in the network in a very short test application time. Experiments showed that, although working at higher abstraction levels, the method has a very high coverage for logic-level structural faults. The test configurations were modified to get a much shorter test time. In addition, the work proposed a set of Design-for-Testability (DfT) techniques for application of test patterns from the external boundary of a Network-on-a-Chip (NoC). The work presented in this thesis has been published in a journal and presented in several international conferences.

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