Adaptive Look Ahead algorithm for 2-D mesh NoC

The existing System on Chip (SoC) design will soon become a critical bottle neck in chip performance with its inability to scale its communication network effectively with decreasing feature sizes and increasing number of transistors. The Network on Chip (NoC) has been recognized as the next evolutionary step to tackle these issues by using an intelligent and common communication network between all the different components within chip. In this paper we propose a new routing algorithm that uses a combination of a fully adaptive and partial adaptive routing algorithm called Adaptive Look Ahead algorithm. The algorithm decides next two hops within one node to allow quick packet transfer in next node, hence the algorithm only periodically calculates the packets route along the minimal path. Experimental results show that our proposed algorithm has lower latency and higher throughput than existing benchmarks.

[1]  Luca Benini,et al.  Networks on chips - technology and tools , 2006, The Morgan Kaufmann series in systems on silicon.

[2]  Timothy Mattson,et al.  A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[3]  Lionel M. Ni,et al.  Adaptive routing in mesh-connected networks , 1992, [1992] Proceedings of the 12th International Conference on Distributed Computing Systems.

[4]  José Duato,et al.  Region-Based Routing: A Mechanism to Support Efficient Routing Algorithms in NoCs , 2009 .

[5]  Akram Ben Ahmed,et al.  LA-XYZ: Low Latency, High Throughput Look-Ahead Routing Algorithm for 3D Network-on-Chip (3D-NoC) Architecture , 2012, 2012 IEEE 6th International Symposium on Embedded Multicore SoCs.

[6]  Vijay Laxmi,et al.  C-Routing: An adaptive hierarchical NoC routing methodology , 2011, 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip.

[7]  Zhiyi Yu,et al.  A 167-Processor Computational Platform in 65 nm CMOS , 2009, IEEE Journal of Solid-State Circuits.

[8]  Radu Marculescu,et al.  DyAD - smart routing for networks-on-chip , 2004, Proceedings. 41st Design Automation Conference, 2004..

[9]  Ming Li,et al.  DyXY - a proximity congestion-aware deadlock-free dynamic routing method for network on chip , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[10]  William J. Dally,et al.  Principles and Practices of Interconnection Networks , 2004 .

[11]  William J. Dally,et al.  Research Challenges for On-Chip Interconnection Networks , 2007, IEEE Micro.