Novel Verification Framework Combining Structural and OBDD Methods in a Synthesis Environment

This paper presents a new methodology for formal logic verification for combinational circuits. Specifically, a structural approach is used, based on indirect implications derived by using Recursive Learning. This is extended to formulate a hybrid approach where this structural method is used to reduce the complexity of a subsequent functional method based on OBDDs. It is demonstrated how OBDD-based verification can take great advantage of structural preprocessing in a synthesis environment. The experimental results show the effective compromise achieved between memory-efficient structural methods and functional methods. One more advantage of these methods lies in the fact that resources that go into logic synthesis can effectively be reused for verification purposes.

[1]  E. J. Aas,et al.  Quantifying design quality: a model and design experiments , 1992, Proceedings Euro ASIC '92.

[2]  Don E. Ross,et al.  Functional approaches to generating orderings for efficient symbolic representations , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.

[3]  D. Brand.  Verification of large synthesized designs , 1993, ICCAD 1993.

[4]  Premachandran R. Menon,et al.  Multi-level Logic Optimization By Implication Analysis , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[5]  Louise Trevillyan,et al.  Functional comparison of logic designs for VLSI circuits , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[6]  Randal E. Bryant,et al.  Efficient implementation of a BDD package , 1991, DAC '90.

[7]  Robert K. Brayton,et al.  Heuristic Minimization of BDDs Using Don't Cares , 1994, 31st Design Automation Conference.

[8]  Ad J. van de Goor,et al.  Logic synthesis of 100-percent testable logic networks , 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[9]  Daniel Brand.  Verification of large synthesized designs , 1993, ICCAD.

[10]  Alberto L. Sangiovanni-Vincentelli,et al.  PROTEUS : A Logic Verification System for Combinational Circuits , 1986, ITC.

[11]  Albert R. Wang,et al.  Logic verification using binary decision diagrams in a logic synthesis environment , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[12]  Hideo Fujiwara,et al.  On the Acceleration of Test Generation Algorithms , 1983, IEEE Transactions on Computers.

[13]  Richard Rudell.  Dynamic variable ordering for ordered binary decision diagrams , 1993, ICCAD.

[14]  F. Brglez,et al.  A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN , 1985 .

[15]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[16]  Srinivas Devadas,et al.  Probabilistic construction and manipulation of Free Boolean Diagrams , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[17]  Rolf Drechsler,et al.  Efficient Representation and Manipulation of Switching Functions Based on Ordered Kronecker Functional Decision Diagrams , 1994, 31st Design Automation Conference.

[18]  Wolfgang Kunz,et al.  HANNIBAL: An efficient tool for logic verification based on recursive learning , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[19]  H. Fujiwara,et al.  ON THE ACCELERATION OF TEST GENERATION ALGORlTHMS , 1995, Twenty-Fifth International Symposium on Fault-Tolerant Computing, 1995, ' Highlights from Twenty-Five Years'..

[20]  Srinivas Devadas,et al.  Probabilistic construction and manipulation of Free Boolean Diagrams , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).