Multi-objective Architectural Floorplanning for 3D IC

In this chapter, we study the multi-objective micro-architectural floorplanning algorithm for high performance processors implemented in IC. Our floorplanner takes a micro-architectural netlist and determines the dimension as well as the placement of the functional modules into single or multiple device layers while simultaneously achieving high performance and thermal reliability. The traditional design objectives such as area and wirelength are also considered. Our 3D floorplanning algorithm considers the following 3D-specific issues: vertical overlap optimization and bonding-aware layer partitioning. Our hybrid floorplanning approach combines Linear Programming and Simulated Annealing, which is shown to be very effective in obtaining high-quality solutions in short runtime under the multi-objective goals. We provide comprehensive experimental results on making tradeoffs among performance, thermal, area, and wirelength for 3D ICs.

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