Decomposition in Asynchronous Circuit Design

[1]  Roberto Segala.  Quiescence, Fairness, Testing, and the Notion of Implementation (Extended Abstract) , 1993, CONCUR.

[2]  Ralf Wollowski,et al.  Comprehensive Causal Specification of Asynchronous Controller and Arbiter Behaviour , 2000 .

[3]  Tam-Anh Chu.  On the models for designing VLSI asynchronous digital systems , 1986, Integr..

[4]  Charles André,et al.  Structural Transformations Giving B-Equivalent PT-Nets , 1982, European Workshop on Applications and Theory of Petri Nets.

[5]  Alexandre Yakovlev,et al.  Signal Graphs: From Self-Timed to Timed Ones , 1985, PNPM.

[6]  P. Kudva,et al.  A technique for synthesizing distributed burst-mode circuits , 1996, 33rd Design Automation Conference Proceedings, 1996.

[7]  Ralf Wollowski,et al.  CASCADE: A Tool Kernel Supporting a Comprehensive Design Method for Asynchronous Controllers , 2000, ICATPN.

[8]  Nancy A. Lynch,et al.  Distributed Algorithms , 1992, Lecture Notes in Computer Science.

[9]  Luciano Lavagno,et al.  On the models for asynchronous circuit behaviour with OR causality , 1996, Formal Methods Syst. Des..

[10]  Jo C. Ebergen,et al.  Arbiters: An Exercise in Specifying and Decomposing Asynchronously Communicating Components , 1992, Sci. Comput. Program..

[11]  Luciano Lavagno,et al.  OR Causality: Modelling and Hardware Implementation , 1994, Application and Theory of Petri Nets.

[12]  S. Wenct.  Using Petri Nets in the Design Process for Interacting Asynchronous Sequential Circuits , 1977 .

[13]  Alex Kondratyev,et al.  Synthesis Method in Self-Timed Design Decompositional Approach , 1993 .

[14]  Luciano Lavagno,et al.  Petrify: A Tool for Manipulating Concurrent Specifications and Synthesis of Asynchronous Controllers (Special Issue on Asynchronous Circuit and System Design) , 1997 .

[15]  Tam-Anh Chu,et al.  Synthesis of self-timed VLSI circuits from graph-theoretic specifications , 1987 .

[16]  Hugo De Man,et al.  A generalized signal transition graph model for specification of complex interfaces , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[17]  Ralf Wollowski,et al.  Controller Implementation by Communicating Asynchronous Sequential Circuits Generated from a Petri Net Specification of Required Behavior , 1992, Synthesis for Control Dominated Circuits.

[18]  David L. Dill,et al.  Trace theory for automatic hierarchical verification of speed-independent circuits , 1989, ACM distinguished dissertations.

[19]  Roberto Segala,et al.  Quiescence, Fairness, Testing, and the Notion of Implementation , 1997, Inf. Comput..