Cost reduction and evaluation of temporary faults detecting technique

IC technologies are approaching the ultimate limits of silicon in terms of channel width, power supply and speed. By approaching these limits, circuits are becoming increasingly sensitive to noise, which will result in unacceptable rates of soft-errors. Furthermore, defect behavior is becoming increasingly complex resulting in increasing number of timing faults that can escape detection by fabrication testing. Thus, fault tolerant techniques will become necessary even for commodity applications. This work considers the implementation and improvements of a new soft error and timing error detecting technique based on time redundancy. Arithmetic circuits were used as test vehicle to validate the approach. Simulations and performance evaluations of the proposed detection technique were made using time and logic simulators. The obtained results show that detection of such temporal faults can be achieved by means of meaningful hardware and performance cost.

[1]  Earl E. Swartzlander,et al.  Computer Arithmetic , 1980 .

[2]  Tack-Don Han,et al.  Fast area-efficient VLSI adders , 1987, 1987 IEEE 8th Symposium on Computer Arithmetic (ARITH).

[3]  James L. Massey,et al.  Review of 'Error-Correcting Codes, 2nd edn.' (Peterson, W. W., and Weldon, E. J., Jr.; 1972) , 1973, IEEE Trans. Inf. Theory.

[4]  Cecilia Metra,et al.  On-line detection of logic errors due to crosstalk, delay, and transient faults , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[5]  W. W. Peterson.  On Checking an Adder , 1958, IBM J. Res. Dev..

[6]  Kai Hwang,et al.  Computer arithmetic: Principles, architecture, and design , 1979 .

[7]  Michael Nicolaidis,et al.  A CAD framework for generating self-checking multipliers based on residue codes , 1999, Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078).

[8]  Harold S. Stone,et al.  A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations , 1973, IEEE Transactions on Computers.

[9]  Kamran Eshraghian,et al.  Principles of CMOS VLSI Design: A Systems Perspective , 1985 .

[10]  Algirdas Avizienis,et al.  Arithmetic Algorithms for Error-Coded Operands , 1973, IEEE Transactions on Computers.

[11]  Edward J. McCluskey,et al.  On-line delay testing of digital circuits , 1994, Proceedings of IEEE VLSI Test Symposium.

[12]  H. T. Kung,et al.  A Regular Layout for Parallel Adders , 1982, IEEE Transactions on Computers.

[13]  Jack Sklansky,et al.  Conditional-Sum Addition Logic , 1960, IRE Trans. Electron. Comput..

[14]  Elizabeth M. Rudnick,et al.  A fast and accurate gate-level transient fault simulation environment , 1993, FTCS-23 The Twenty-Third International Symposium on Fault-Tolerant Computing.

[15]  Michael Nicolaidis.  Time redundancy based soft-error tolerance to rescue nanometer technologies , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).

[16]  M. Baze,et al.  Attenuation of single event induced pulses in CMOS combinational logic , 1997 .