A type-safe arbitrary precision arithmetic portability layer for HLS tools

Recent studies have shown that High-Level Synthesis (HLS) is an efficient way to design operators for floating-point arithmetic, or for emerging alternative formats such as posits. However, HLS tools support different supersets of different subsets of the C language -- for example, support for arbitrary-sized bit vectors may be provided through vendor-specific data-type libraries such as ac_int, ap_int, or int1 to int64, while others only support the standard C integer types. This is a problem when carefully tuning an operator's internal data-path, as there is no portable HLS standard for arbitrary width integers, and vendor libraries may introduce implicit casts and extensions that can hide subtle bugs. Each vendor also offers varying support for important operator-building primitives, such as platform-optimized leading-zero count. To address such problems, this work introduces Hint (hardware integer), a header-only compatibility layer offering a consistent and comprehensive interface to signed and unsigned arbitrary-sized integers. To avoid bugs Hint is strongly typed, requiring exact matching of expression widths and types -- this type-checking is performed statically using the C++ template system, and adds no overhead at synthesis time. The current implementation wraps ac_int and ap_int with no performance or resource overhead when synthesized on Xilinx or Intel FPGAs. It also offers a Boost::multiprecision backend for fast simulation. Hint is open-source and extensible, and aims to provide an optimized superset of existing library primitives. This work is evaluated with arithmetic operators useful when implementing floating-point and posit operators (shifter, leading zero counter, fused shifter+sticky) deployed using two mainstream HLS tools (Xilinx VivadoHLS, and IntelHLS). A complete posit adder operator has also been written using Hint, showing no overhead when compared to the original operator written for Xilinx FPGAs.

[1]  James O. Coplien,et al.  Curiously recurring template patterns , 1995 .

[2]  Florent de Dinechin,et al.  Bridging high-level synthesis and application-specific arithmetic: The case study of floating-point summations , 2017, 2017 27th International Conference on Field Programmable Logic and Applications (FPL).

[3]  Satoshi Matsuoka,et al.  Hardware Implementation of POSITs and Their Application in FPGAs , 2018, 2018 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW).

[4]  Florent de Dinechin,et al.  Designing Custom Arithmetic Data Paths with FloPoCo , 2011, IEEE Design & Test of Computers.

[5]  Miriam Leeser,et al.  Advanced Components in the Variable Precision Floating-Point Library , 2006, 2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

[6]  Jason Helge Anderson,et al.  LegUp: high-level synthesis for FPGA-based processor/accelerator systems , 2011, FPGA '11.

[7]  Jason Helge Anderson,et al.  High-level synthesis of software-customizable floating-point cores , 2018, 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[8]  David B. Thomas Templatised Soft Floating-Point for High-Level Synthesis , 2019, 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

[9]  Adrien Prost-Boucle,et al.  Fast and standalone Design Space Exploration for High-Level Synthesis under resource constraints , 2014, J. Syst. Archit..

[10]  Yu Ting Chen,et al.  A Survey and Evaluation of FPGA High-Level Synthesis Tools , 2016, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  Florent de Dinechin,et al.  Evaluating the Hardware Cost of the Posit Number System , 2019, 2019 29th International Conference on Field Programmable Logic and Applications (FPL).