Burn-in temperature projections for deep sub-micron technologies

Burn-in faces significant challenges in recent CMOS technologies. The self-generated heat of each IC in a burn-in environment contributes to larger currents that can lead to further increase in junction temperatures, possible thermal run away, and yield-loss of good parts. Calculations show that the junction temperature is increasing by 1.45X/generation. This paper estimates the increase in junction temperature with scaling and discusses the optimal burn-in temperature with scaling. Our research indicates that the burn-in temperature must also be reduced with technology scaling. The impact on commercial burn-in ovens is also described.

[1]  Shekhar Beaverton Borkar.  Low-voltage design for portable systems - leakage reduction in digital CMOS circuits , 2002 .

[2]  Stephen H. Gunther,et al.  Managing the Impact of Increasing Microprocessor Power Consumption , 2001 .

[3]  D. P. Vallett,et al.  Finding fault with deep-submicron ICs , 1997 .

[4]  Mary Jane Irwin,et al.  Transistor sizing for low power CMOS circuits , 1996, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  W. Wondrak.  Physical limits and lifetime limitations of semiconductor devices at high temperatures , 1999 .

[6]  Niccolò Rinaldi,et al.  On the modeling of the transient thermal behavior of semiconductor devices , 2001 .

[7]  Robert H. Dennard,et al.  CMOS scaling for high performance and low power-the next ten years , 1995, Proc. IEEE.

[8]  Kwang-Pyuk Suh,et al.  1 GHz microprocessor integration with high performance transistor and low RC delay , 1999 .

[9]  Gerard Ghibaudo,et al.  Time to breakdown and voltage to breakdown modeling for ultra-thin oxides (Tox<32/spl Aring/) , 2001, 2001 IEEE International Integrated Reliability Workshop. Final Report (Cat. No.01TH8580).

[10]  H. Nambu,et al.  UX6-100 nm generation CMOS integration technology with Cu/low-k interconnect , 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

[11]  Kwang-Pyuk Suh,et al.  1 GHz microprocessor integration with high performance transistor and low RC delay , 1999, International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318).

[12]  N. F. Dean,et al.  Characterization of a thermal interface material for burn-in application , 2000, ITHERM 2000. The Seventh Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (Cat. No.00CH37069).

[13]  D. Talbot.  Paper 4 , 2022 .

[14]  G. Kroman.  Thermal management of a C4/CBGA interconnect technology for a high-performance RISC microprocessor: the Motorola PowerPC 620/sup TM/ microprocessor , 1996, 1996 Proceedings 46th Electronic Components and Technology Conference.

[15]  S. Rusu,et al.  Trends and challenges in VLSI technology scaling towards 100 nm , 2002, Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design.

[16]  Sung-Mo Kang,et al.  A chip-level electrothermal simulator for temperature profile estimation of CMOS VLSI chips , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[17]  David J. Frank,et al.  Power-constrained CMOS scaling limits , 2002, IBM J. Res. Dev..

[18]  R. Viswanath.  Thermal Performance Challenges from Silicon to Systems , 2000 .

[19]  Stefan Rusu.  Trends and challenges in VLSI technology scaling towards 100nm , 2001, Proceedings of the 27th European Solid-State Circuits Conference.

[20]  Chia-Pin Chiu,et al.  Novel thermal validation metrology based on non-uniform power distribution for Pentium(R) III Xeon/sup TM/ cartridge processor design with integrated level two cache , 2001, 2001 Proceedings. 51st Electronic Components and Technology Conference (Cat. No.01CH37220).

[21]  A.W. Righter,et al.  CMOS IC reliability indicators and burn-in economics , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[22]  Way Kuo,et al.  Burn-in effect on yield , 2000 .

[23]  Shekhar Y. Borkar,et al.  Design challenges of technology scaling , 1999, IEEE Micro.

[24]  Niccolò Rinaldi.  Thermal analysis of solid-state devices and circuits: an analytical approach , 2000 .

[25]  Paul A. Reed,et al.  A 250-MHz 5-W PowerPC microprocessor with on-chip L2 cache controller , 1997 .

[26]  A. Ono,et al.  A 100 nm node CMOS technology for practical SOC application requirement , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[27]  P. Lall,et al.  Tutorial: temperature as an input to microelectronics-reliability models , 1996, IEEE Trans. Reliab..

[28]  Sung-Mo Kang,et al.  iTEM: a temperature-dependent electromigration reliability diagnosis tool , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[29]  Wei Jin,et al.  High performance 50 nm CMOS devices for microprocessor and embedded processor core applications , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[30]  J. B. Bowles,et al.  A survey of reliability-prediction procedures for microelectronic devices , 1992 .

[31]  W. R. Hunter,et al.  Experimental evidence for voltage driven breakdown models in ultrathin gate oxides , 2000, 2000 IEEE International Reliability Physics Symposium Proceedings. 38th Annual (Cat. No.00CH37059).

[32]  S. Thompson.  MOS Scaling: Transistor Challenges for the 21st Century , 1998 .

[33]  Mike Alexander,et al.  Thermal management system for high performance PowerPC/sup TM/ microprocessors , 1997, Proceedings IEEE COMPCON 97. Digest of Papers.

[34]  E. S. Schlig,et al.  Thermal properties of very fast transistors , 1970 .