High Performance Carry Skip Adder using Reversible Logic

The increasing demand for low-power VLSI can be addressed at different steps of VLSI design cycle, such as the architectural, circuit, layout, and the process technology level. At the circuit design step, considerable potential for power saving exists by means of proper choice of a logic style for implementing circuits. The is because all the important parameters governing power dissipation- switching capacitance, transition activity, and shortcircuit currents-are strongly influenced by the chosen logic style. The carry-skip adder reduces the time needed to propagate the carry by skipping over groups of consecutive adder stages, is known to be comparable in speed to the carry-look ahead technique while it uses less logic area and less power. We will design 8-bit Carry Skip Adder by using T-Spice v13.0 for 1v, 90nm technology.