Power-density aware floorplanning for reducing maximum on-chip temperature

With microprocessor power densities escalating rapidly as technology scales below 100nm level, there is an urgent need for developing innovative cooling solutions. In this paper, we introduce the concept of power-density aware thermal floorplanning and demonstrate its efficacy in reducing maximum on-chip temperature. We argue that Compact Thermal Model (CTM) based floorplanners will be hard pressed by time-to-market pressure for placing circuits having large number of modules. To circumvent this problem, we present a novel power-density aware floorplanning technique for reducing the maximum on-chip temperature that has much less runtime compared to CTM based floorplanners. Based on our method we develop a floorplanner that we name COOLER. Instead of using the conventional Simulated Annealing procedure, COOLER uses a highly efficient Multiobjective Evolutionary Algorithm to generate the Pareto-front. Experimental results on MCNC benchmark demonstrate that COOLER is 11x-146x faster than HOTFLOORPLAN. We use HOTSPOT for thermal simulation of the layouts produced by COOLER. Finally, we validate our method by demonstrating that HOTFLOORPLAN solutions lie on the Pareto-front generated by COOLER. It was found that by careful arrangement of components at the architecture level, the average reduction in peak temperature produced by HOTFLOORPLAN and COOLER was 15.1°C and 15.3°C respectively.