A low-voltage, Low-Power 4-bit BCD adder, designed using the Clock Gated Power Gating, and the DVT scheme

This paper proposes a Low-Power, Energy Efficient 4bit Binary Coded Decimal (BCD) adder design where the conventional 4-bit BCD adder has been modified with the Clock Gated Power Gating Technique. Moreover, the concept of DVT (Dual-vth) scheme has been introduced while designing the full adder blocks to reduce the Leakage Power, as well as, to maintain the overall performance of the entire circuit. The reported architecture of 4-bit BCD adder is designed using 45 nm technology and it consumes 1.384 μWatt of Average Power while operating with a frequency of 200 MHz, and a Supply Voltage (Vdd) of 1 Volt. The results obtained from different simulation runs on SPICE, indicate the superiority of the proposed design compared to the conventional 4-bit BCD adder. Considering the product of Average Power and Delay, for the operating frequency of 200 MHz, a fair 47.41% reduction compared to the conventional design has been achieved with this proposed scheme.

[1]  Enrico Macii,et al.  Power Efficient Variability Compensation Through Clustered Tunable Power-Gating , 2011, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[2]  Massoud Pedram,et al.  Coarse-Grain MTCMOS Sleep Transistor Sizing Using Delay Budgeting , 2008, 2008 Design, Automation and Test in Europe.

[3]  Sung-Mo Kang,et al.  CMOS digital integrated circuits , 1995 .

[4]  Mark C. Johnson,et al.  Design and optimization of dual-threshold circuits for low-voltage low-power applications , 1999, IEEE Trans. Very Large Scale Integr. Syst..

[5]  Yin-Tsung Hwang,et al.  A Novel High-Speed and Energy Efficient 10-Transistor Full Adder Design , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.

[6]  Ankur Srivastava,et al.  Leakage Control Through Fine-Grained Placement and Sizing of Sleep Transistors , 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  A. A. Bayrakci,et al.  An Efficient Vanishing Point Detection by Clustering on the Normalized Unit Sphere , 2007 .

[8]  Kaushik Roy,et al.  Mixed-Vth (MVT) CMOS circuit design methodology for low power applications , 1999, DAC '99.

[9]  Wolfgang Henseler,et al.  Digital Design , 2003 .

[10]  E. Abu-Shama,et al.  A new cell for low power adders , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[11]  M.A. Erle,et al.  Potential speedup using decimal floating-point hardware , 2002, Conference Record of the Thirty-Sixth Asilomar Conference on Signals, Systems and Computers, 2002..

[12]  Ahmet Akkas,et al.  Reduced Delay BCD Adder , 2007, 2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors (ASAP).

[13]  Mark C. Johnson,et al.  Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks , 1998, ISLPED '98.

[14]  Ankur Srivastava,et al.  Leakage Control Through Fine-Grained Placement and Sizing of Sleep Transistors , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[15]  Michael J. Schulte,et al.  A survey of hardware designs for decimal arithmetic , 2010, IBM J. Res. Dev..

[16]  S. Akashe,et al.  A novel high-performance CMOS 1 bit full-adder cell , 2013, 2013 7th International Conference on Intelligent Systems and Control (ISCO).

[17]  Luca Benini,et al.  Design of a Flexible Reactivation Cell for Safe Power-Mode Transition in Power-Gated Circuits , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[18]  Michael F. Cowlishaw,et al.  Decimal floating-point: algorism for computers , 2003, Proceedings 2003 16th IEEE Symposium on Computer Arithmetic.

[19]  P. SaiPhaneendra,et al.  A Unified Architecture for BCD and Binary Adder/Subtractor , 2011, 2011 14th Euromicro Conference on Digital System Design.

[20]  Haomin Wu,et al.  A new design of the CMOS full adder , 1992 .

[21]  Lei He,et al.  Distributed sleep transistor network for power reduction , 2003, DAC '03.

[22]  N. Ranganathan,et al.  A new reversible design of BCD adder , 2011, 2011 Design, Automation & Test in Europe.

[23]  Chulwoo Kim,et al.  CMOS Digital Integrated Circuits: Analysis & Design, 4th Edition , 2014 .

[24]  C. Chrisjin Gnana Suji,et al.  Performance analysis of power gating designs in low power VLSI circuits , 2011, 2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies.

[25]  Luca Benini,et al.  Timing-driven row-based power gating , 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).

[26]  Srinivas Katkoori,et al.  High level techniques for leakage power estimation and optimization in vlsi asics , 2003 .

[27]  V. Sumathy,et al.  FPGA Implementation of Low Power Hardware Efficient Flagged Binary Coded Decimal Adder , 2012 .

[28]  Wilfried Buchholz.  Fingers or fists? (the choice of decimal or binary representation) , 1959, CACM.

[29]  David Y. Y. Yun,et al.  RBCD: redundant binary coded decimal adder , 1989 .

[30]  Sayan Chatterjee,et al.  Design and Analysis of a Robust, High Speed, Energy Efficient 18 Transistor 1-bit Full Adder Cell, Modified with the Concept of MVT Scheme , 2012, 2012 International Symposium on Electronic System Design (ISED).

[31]  Mark C. Johnson,et al.  SUBTHRESHOLD LEAKAGE CONTROL BY MULTIPLE CHANNEL LENGTH CMOS (McCMOS) , 1997 .