Developing a decoupling methodology with SPICE for multilayer printed circuit boards

As CPU and bus speeds increase in high end workstation computer systems, signal integrity and EMI issues related to delta-I noise (caused by the current demands of the many fast switching devices on the PCB) require serious consideration during the design process. Historically, decoupling caps have been deployed "randomly" about the PCB in an attempt to mitigate this noise. However, as clock speeds increase beyond 500 MHz and rise times decrease to less than 300 psec, the design of power bus decoupling on multilayer boards requires close attention. Issues such as interplane capacitance, decoupling capacitor placement values and quantities, interconnect inductance as well as power bus resonances all need to be carefully manipulated and controlled in order to achieve the most cost effective and robust electromagnetically compatible products. In this paper a SPICE model is employed to examine the impedance of a typical power bus on a multilayer PCB. This impedance is calculated at numerous points (or nodes) around the board with respect to the noise sources and as a result the choice and quantity of decoupling capacitors as well as placement information and the resulting impact on the power supply impedance is evaluated.