Advanced mask-to-mask overlay analysis for next generation technology node reticles

Double Patterning Lithography (DPL) for next-generation wafer exposure is placing greater demands on the requirements for pattern placement accuracy on photomasks: the DPL mask pair must now meet the pattern placement specifications that a single mask was required to meet in previous generations. As a result, each mask in the mask pair must individually conform to much tighter mask registration specs. Minimizing all sources of systematic overlay error has become critical. In addition, the mask-to-mask overlay between the two masks comprising the DPL pair must be measured-a methodology shift from the current practice of referencing mask registration error only to design data. Characterizing mask-to-mask overlay error requires the ability to measure pattern placement errors using in-die structures on reticle pairs. Today's analysis methods do not allow for comparison of registration maps based on different site locations. This gap has created a lack of information about the true overlay impact of mask-to-mask registration errors on masks with few or no common features. A new mask-to-mask overlay analysis method is demonstrated that provides new flexibility for mask-to-mask comparison. This new method enables mask manufacturers to meet fab requirements for DPL, and it enables semiconductor manufacturers to verify if overlay deviations are within acceptable limits.