Multifault testability of delay-testable circuits
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[1] Premachandran R. Menon,et al. Multifault and delay-fault testability of multilevel circuits , 1995, J. Electron. Test..
[2] James E. Smith. On the Existence of Combinational Logic Circuits Exhibiting Multiple Redundancy , 1978, IEEE Transactions on Computers.
[3] Kurt Keutzer,et al. On properties of algebraic transformations and the synthesis of multifault-irredundant circuits , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[4] S. M. Reddy,et al. On the design of path delay fault testable combinational circuits , 1990, [1990] Digest of Papers. Fault-Tolerant Computing: 20th International Symposium.
[5] Sudhakar M. Reddy,et al. On Delay Fault Testing in Logic Circuits , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[6] Robert K. Brayton,et al. Equivalence of robust delay-fault and single stuck-fault test generation , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.
[7] Robert K. Brayton,et al. MIS: A Multiple-Level Logic Optimization System , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[8] Vishwani D. Agrawal,et al. Multiple fault detection in two-level multi-output circuits , 1992, J. Electron. Test..
[9] Gordon L. Smith,et al. Model for Delay Faults Based upon Paths , 1985, ITC.
[10] Sharad Malik,et al. A synthesis-based test generation and compaction algorithm for multifaults , 1991, 28th ACM/IEEE Design Automation Conference.
[11] Zvi Kohavi,et al. Detection of Multiple Faults in Combinational Logic Networks , 1972, IEEE Transactions on Computers.
[12] Gernot Metze,et al. A New Representation for Faults in Combinational Digital Circuits , 1972, IEEE Transactions on Computers.
[13] Kurt Keutzer,et al. Synthesis of robust delay-fault-testable circuits: theory , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..