Two-stage thermal-aware scheduling of task graphs on 3D multi-cores exploiting application and architecture characteristics
暂无分享,去创建一个
[1] Rong Ge,et al. Power and energy profiling of scientific applications on distributed systems , 2005, 19th IEEE International Parallel and Distributed Processing Symposium.
[2] Arvind Kumar,et al. Three-dimensional integrated circuits , 2006, IBM J. Res. Dev..
[3] Amit Kumar Singh,et al. Thermal-aware mapping of streaming applications on 3D Multi-Processor Systems , 2013, The 11th IEEE Symposium on Embedded Systems for Real-time Multimedia.
[4] Kalyanmoy Deb,et al. A fast and elitist multiobjective genetic algorithm: NSGA-II , 2002, IEEE Trans. Evol. Comput..
[5] Jun Yang,et al. Thermal-Aware Task Scheduling for 3D Multicore Processors , 2010, IEEE Transactions on Parallel and Distributed Systems.
[6] Charles H.-P. Wen,et al. Thermal-Constrained Task Scheduling on 3-D Multicore Processors for Throughput-and-Energy Optimization , 2015, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[7] Amit Kumar Singh,et al. Thermal-aware task scheduling for peak temperature minimization under periodic constraint for 3D-MPSoCs , 2014, 2014 25nd IEEE International Symposium on Rapid System Prototyping.
[8] Li Shang,et al. Accurate Temperature-Dependent Integrated Circuit Leakage Power Estimation is Easy , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.
[9] Qing Wu,et al. Thermal-aware job allocation and scheduling for three dimensional chip multiprocessor , 2010, 2010 11th International Symposium on Quality Electronic Design (ISQED).
[10] Krishnendu Chakrabarty,et al. An online thermal-constrained task scheduler for 3D multi-core processors , 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[11] S.L. Wright,et al. 3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias , 2006, IEEE Journal of Solid-State Circuits.
[12] Ya-Shu Chen,et al. Thermal-aware real-time task scheduling for three-dimensional multicore chip , 2012, SAC '12.
[13] Lei He,et al. Temperature and supply Voltage aware performance and power modeling at microarchitecture level , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[14] Cody Hao Yu,et al. Thermal-Aware On-Line Scheduler for 3-D Many-Core Processor Throughput Optimization , 2014, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[15] Meikang Qiu,et al. Thermal-aware task scheduling in 3D chip multiprocessor with real-time constrained workloads , 2013, TECS.
[16] David Blaauw,et al. Statistical estimation of leakage current considering inter- and intra-die process variation , 2003, ISLPED '03.
[17] Wei Zhang,et al. Thermal-aware task scheduling for 3D-network-on-chip: A Bottom-to-Top scheme , 2014, 2014 International Symposium on Integrated Circuits (ISIC).