Optical receivers in ECL for 1GHz parallel links

ABSTRACT An optical receiver array containing 8 channels for optical interconnections is implemented in a silicon1tm bipolar technology. It operates up to lGbit/s with an overall delay of 1.4ns between optical signalinput and full ECL level output. The fully DC-coupled channels need a photocurrent of 7tA to switchthe logical level. Chip area and power consumption per channel correspond to 4 regular ECL gates. 1. INTRODUCTIONReceiver arrays for optical interconnects differ in significant ways from receivers for fiber optical communication. Receivers for fiber communication are commonly well optimized with relatively largeelectronic circuits incorporating a number of different features and are often built on more than one chipand with several discrete components. Receivers for optical interconnects, however, have to be simple,compact and low power circuits. They are closely spaced in arrays combined with VLSI-circuits, either inhybrid or fully integrated form. In order to allow transmission of unformated data the signal path has to befully DC-coupled.The main quality is speed in terms of maximum allowable bit rate and time delay between optical signalinput and digital level output. Amplitude dependent delays are not avoidable in a DC-coupled system butcan be kept low by carefully optimizing the receiver stages. It is desirable to operate at low light intensities,but the sensitivity is of lower priority than in a communication receiver. Requirements concerning speedof response, delays, dynamic range and sensitivity are to be met with strong emphasis on simplicity, smallchip area and low power consumption.Possible applications of optical interconnections lie in the high speed processor field. For that reason wechoosed silicon bipolar technology for implementation of the receivers. The achievable complexity ofsilicon bipolar technology has reached the 100k-gate range1' and is therefore suited to build LSI circuitswith optical interconnections.The receiver array described in this paper is based on the commercially available CD1O14 gate array ofPlessey fabricated in a 1itm silicon bipolar process21 and has been designed for a bit rate of lGBit/s. From