HITEC: a test generation package for sequential circuits

Presents HITEC, a sequential circuit test generation package to generate test patterns for sequential circuits, without assuming the use of scan techniques or a reset state. Several new techniques are introduced to improve the performance of test generation. A targeted D element technique is presented, which greatly increases the number of possible mandatory assignments and reduces the over-specification of state variables which can sometimes result when using a standard PODEM algorithm. A technique to use the state knowledge of previously generated vectors for state justification, without the memory overhead of a state transition diagram is presented. For faults that were aborted during the standard test generation phase, knowledge that was gained about fault propagation, by the fault simulator, is used. These techniques, when used together, produce the best published results for the ISCAS89, sequential benchmark circuits.<<ETX>>

[1]  Michael H. Schulz,et al.  ESSENTIAL: an efficient self-learning test pattern generation algorithm for sequential circuits , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[2]  W.-T. Cheng,et al.  The BACK algorithm for sequential test generation , 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.

[3]  M. Ray Mercer,et al.  A Topological Search Algorithm for ATPG , 1987, 24th ACM/IEEE Design Automation Conference.

[4]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[5]  Peter Muth,et al.  A Nine-Valued Circuit Model for Test Generation , 1976, IEEE Transactions on Computers.

[6]  Janak H. Patel,et al.  Proofs: a fast, memory efficient sequential circuit fault simulator , 1991, DAC '90.

[7]  Wu-Tung Cheng,et al.  SPLIT circuit model for test generation , 1988, 25th ACM/IEEE, Design Automation Conference.Proceedings 1988..

[8]  Alberto L. Sangiovanni-Vincentelli,et al.  Test generation for sequential circuits , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Ralph Marlett,et al.  EBT: A Comprehensive Test Generation Technique for Highly Sequential Circuits , 1978, 15th Design Automation Conference.

[10]  L. H. Goldstein,et al.  SCOAP: Sandia Controllability/Observability Analysis Program , 1988, 17th Design Automation Conference.

[11]  Hideo Fujiwara,et al.  On the Acceleration of Test Generation Algorithms , 1983, IEEE Transactions on Computers.

[12]  Srinivas Devadas,et al.  Test generation for highly sequential circuits , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[13]  Janak H. Patel,et al.  Accurate logic simulation in the presence of unknowns , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[14]  Prabhakar Goel,et al.  An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits , 1981, IEEE Transactions on Computers.

[15]  Wilfried Daehn,et al.  Accelerated test pattern generation by cone-oriented circuit partitioning , 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

[16]  Robert E. Tarjan,et al.  Finding Dominators in Directed Graphs , 1974, SIAM J. Comput..

[17]  Ralph A. Marlett.  An Effective Test Generation System for Sequential Circuits , 1986, DAC 1986.

[18]  Michael H. Schulz,et al.  SOCRATES: a highly efficient automatic test pattern generation system , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[19]  Michael H. Schulz,et al.  Advanced automatic test pattern generation and redundancy identification techniques , 1988, [1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.