A 4.9-dB NF 53.5–62-GHz micro-machined CMOS wideband LNA with small group-delay-variation

A 53.5–62-GHz wideband CMOS low-noise amplifier (LNA) with excellent phase linearity property is reported. Current-sharing technique is adopted to reduce power dissipation. The LNA (STD LNA) consumed 29.1 mW and achieved input return loss (S11) of −10.3∼ −19.5 dB, output return loss (S<inf>22</inf>) of −13.8∼ −27.8 dB, forward gain (S<inf>21</inf>) of 8.1∼ 11.1 dB, and reverse isolation (S<inf>12</inf>) of −49.9∼ −60.2 dB over the 53.5–62-GHz-band. The minimum NF (NF<inf>min</inf>) is 5.4 dB at 62 GHz. To reduce the substrate loss, the CMOS process compatible backside inductively-coupled-plasma (ICP) deep trench technology is used to remove the silicon underneath the LNA. After the ICP etching, the LNA (ICP LNA) achieved maximum S<inf>21</inf> (S<inf>21-max</inf>) of 13.2 dB, 2.1 dB higher than that (11.1 dB) of the STD LNA. In addition, the ICP LNA achieved NF<inf>min</inf> of 4.9 dB, 0.5 dB lower than that (5.4 dB) of the STD LNA. These results demonstrate the proposed LNA architecture in conjunction with the backside ICP technology is very promising for 60-GHz-band RFIC applications.

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