Test generation for BiCMOS circuits

Stuck-ON faults in BiCMOS devices result in an enhanced I/sub DDQ/. Stuck-OPEN faults exhibit both sequential behavior and delay faults. Test generation is considered for stuck-ON and stuck-OPEN faults in BiCMOS circuits. A procedure for obtaining test vectors/sequences for testing of faults manifesting as enhanced I/sub DDQ/ delay faults and sequential behavior is presented. The procedure involves activating a conduction path to obtain test vectors/sequences. The resulting test vectors obtained for single stuck-ON faults are also applicable to multiple stuck-ON faults. The scheme provides robust test sequences with unity Hamming distance for testing of delay faults and sequential behavior in BiCMOS circuits.<<ETX>>

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