FPGA Implementation of a Phase-Aware Single-Channel Speech Enhancement System

This paper presents a real-time architecture of an improved single-channel speech enhancement system based on phase-aware multi-band complex spectral subtraction. Using the proposed technique, the short-time spectral magnitude of the clean speech signal is estimated by considering the spectral phase of the speech and noise signal components. Moreover, the estimated spectral phase of the clean speech signal is also utilized for signal reconstruction in the time domain. The proposed system is made of the basic preprocessing module followed by an short-time Fourier transform analyzer, a noise power estimator based on improved minima controlled recursive array, a phase estimator unit and an overlap-add synthesis unit. The proposed architecture is implemented on a Field Programmable Gate Array (FPGA) using the Xilinx ISE tool. The overall resource utilization and the maximum operating frequency are also computed for a Virtex-6 FPGA chip. It has been experimentally shown that the proposed speech enhancement framework performs better than the other existing standard benchmark methods in terms of various quality and intelligibility assessment metrics.