Robust self concurrent test of linear digital systems

The concurrent fault detection methods are generally based either explicitly or implicitly, on the use of redundancy. This paper presents a novel methodology for concurrent fault detection in linear digital systems. The basic principle of approach is the use of implicit analytical redundancy relations, i.e. relations between the measurement available variables. The robustness requirement of the redundancy relations guarantees a maximal sensitivity of the concurrent detector against fault and minimal sensitivity, towards noise. Techniques for designing fault detection circuitry using optimal redundancy relations are discussed. Error detection capabilities of the scheme proposed in this work are efficient for a very large class of linear digital signal processor. The test circuit obtained for concurrent fault detector implementation is still very reasonable.

[1]  Abhijit Chatterjee,et al.  The Design of Fault-Tolerant Linear Digital State Variable Systems: Theory and Techniques , 1993, IEEE Trans. Computers.

[2]  Jacob A. Abraham,et al.  Fault-Tolerant FFT Networks , 1988, IEEE Trans. Computers.

[3]  Ahmad ABDELHAY,et al.  Analytical redundancy based approach for concurrent fault detection in linear digital systems , 2000, Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646).

[4]  Abhijit Chatterjee,et al.  On-line fault detection in DSP circuits using extrapolated checksums with minimal test points , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[5]  A. Willsky,et al.  Analytical redundancy and the design of robust failure detection systems , 1984 .

[6]  Frederic Truchetet Traitement linéaire du signal numérique , 1998 .

[7]  Paul M. Frank,et al.  Fault diagnosis in dynamic systems using analytical and knowledge-based redundancy: A survey and some new results , 1990, Autom..

[8]  Suku Nair,et al.  Real-Number Codes for Bault-Tolerant Matrix Operations On Processor Arrays , 1990, IEEE Trans. Computers.

[9]  Prithviraj Banerjee,et al.  Algorithms-Based Fault Detection for Signal Processing Applications , 1990, IEEE Trans. Computers.

[10]  Jacob A. Abraham,et al.  Algorithm-Based Fault Tolerance for Matrix Operations , 1984, IEEE Transactions on Computers.

[11]  Franklin T. Luk,et al.  A Linear Algebraic Model of Algorithm-Based Fault Tolerance , 1988, IEEE Trans. Computers.

[12]  J.A. Abraham,et al.  Fault-tolerant matrix arithmetic and signal processing on highly concurrent computing structures , 1986, Proceedings of the IEEE.