A Mobility-Based Time Reference

As shown in Chap. 2, Wireless Sensor Network (WSN) nodes must be equipped with fully integrated time references with an accuracy of the order of 1% and a power consumption lower than 100 μW. Recently, much work has been devoted to implementing fully integrated time references in standard microelectronic technologies. As shown in Chap. 3, the inaccuracy of several of them is low enough for WSN applications, but they need either a too high power consumption or a very accurate process characterization, with a consequent limitation of their practical use.

[1]  Kaushik Roy,et al.  Gate leakage reduction for scaled devices using transistor stacking , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[2]  Maarten Vertregt,et al.  Characterization of systematic MOSFET current factor mismatch caused by metal CMP dummy structures , 2001 .

[3]  R. A. Blauschild.  An integrated time reference , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.

[4]  D. E. Burk,et al.  MOSFET electron inversion layer mobilities-a physically based semi-empirical model for a wide temperature range , 1989 .

[5]  Y. Taur,et al.  Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET's , 1997, IEEE Electron Device Letters.

[6]  Greg Taylor,et al.  Temperature Sensor Design in a High Volume Manufacturing 65nm CMOS Digital Process , 2007, 2007 IEEE Custom Integrated Circuits Conference.

[7]  K. Makinwa,et al.  A Low-Voltage Mobility-Based Frequency Reference for Crystal-Less ULP Radios , 2009, IEEE Journal of Solid-State Circuits.

[8]  B. Nauta,et al.  Analog circuits in ultra-deep-submicron CMOS , 2005, IEEE Journal of Solid-State Circuits.

[9]  Y.W. Li,et al.  A 1.05 V 1.6 mW, 0.45 $^{\circ}$C 3 $\sigma$ Resolution $\Sigma\Delta$ Based Temperature Sensor With Parasitic Resistance Compensation in 32 nm Digital CMOS Process , 2009, IEEE Journal of Solid-State Circuits.

[10]  Willy Sansen,et al.  A CMOS temperature-compensated current reference , 1988 .

[11]  Kofi A. A. Makinwa,et al.  A CMOS smart temperature sensor with a batch-calibrated inaccuracy of ±0.25°C (3σ) from −70°C to 130°C , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[12]  R. Sarpeshkar,et al.  A 10-nW 12-bit accurate analog storage cell with 10-aA leakage , 2004, IEEE Journal of Solid-State Circuits.

[13]  G.C.M. Meijer,et al.  Temperature sensors and voltage references implemented in CMOS technology , 2001, IEEE Sensors Journal.

[14]  Johan H. Huijsing,et al.  Micropower CMOS temperature sensor with digital output , 1996, IEEE J. Solid State Circuits.

[15]  Yannis Tsividis,et al.  Integrated continuous-time filter design - an overview , 1994, IEEE J. Solid State Circuits.

[16]  Kofi A. A. Makinwa,et al.  Effects of packaging and process spread on a mobility-based frequency reference in 0.16-μm CMOS , 2011, 2011 Proceedings of the ESSCIRC (ESSCIRC).

[17]  John A. McNeill,et al.  Jitter in oscillators with 1/f noise sources , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[18]  Y. Tsividis.  Operation and modeling of the MOS transistor , 1987 .

[19]  Wen-Chin Lee,et al.  The Effects of Mechanical Uniaxial Stress on Junction Leakage in Nanoscale CMOSFETs , 2008, IEEE Transactions on Electron Devices.

[20]  Tahir Ghani,et al.  Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors , 2000, 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104).

[21]  M. Vertregt,et al.  Test structures for investigation of metal coverage effects on MOSFET matching , 1997, 1997 IEEE International Conference on Microelectronic Test Structures Proceedings.

[22]  R. Gregor,et al.  On the relationship between topography and transistor matching in an analog CMOS technology , 1992 .