Power, Performance, Area and Cost Analysis of Memory-on-Logic Face-to-Face Bonded 3D Processor Designs

In this paper, we present a power, performance, area and cost (PPAC) analysis for large-scale 3D processor designs based on wafer-to-wafer bonding. From the evaluation of our cost model, we investigate a typically disregarded opportunity in 3D that is area savings due to buffer savings and better routability, offering unexpected cost savings. We explore the viability of this factor with the feedback of a state-of-the-art 3D memory-on-logic implementation flow. We show how this affects the PPAC of full-chip GDS implementations of a large-scale manycore processor design. Experiments show that our memory-on-logic 3D implementation offers 7% silicon area savings, resulting in 53.5% footprint reduction. We also obtain a 40% power-performance-cost improvement compared with 2D counterparts

[1]  Israel Koren,et al.  Defect tolerance in VLSI circuits: techniques and yield analysis , 1998, Proc. IEEE.

[2]  Geert Vandenberghe,et al.  The economic impact of EUV lithography on critical process modules , 2014, Advanced Lithography.

[3]  O. O. Okudur,et al.  Scalable, sub 2μm pitch, Cu/SiCN to Cu/SiCN hybrid wafer-to-wafer bonding technology , 2017, 2017 IEEE International Electron Devices Meeting (IEDM).

[4]  Yuan Xie,et al.  Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[5]  Paola Annoni,et al.  Variance based sensitivity analysis of model output. Design and estimator for the total sensitivity index , 2010, Comput. Phys. Commun..

[6]  D.K. de Vries,et al.  Investigation of gross die per wafer formulas , 2005, IEEE Transactions on Semiconductor Manufacturing.

[7]  Diederik Verkest,et al.  Maintaining Moore’s law: enabling cost-friendly dimensional scaling , 2015, Advanced Lithography.

[8]  Jonathan Balkind,et al.  OpenPiton + Ariane : The First Open-Source , SMP Linux-booting RISC-V System Scaling From One to Many Cores , 2019 .

[9]  A. Ferris-Prabhu.  An algebraic expression to count the number of chips on a wafer , 1989, IEEE Circuits and Devices Magazine.

[10]  Yuan Xie,et al.  System-level cost analysis and design exploration for three-dimensional integrated circuits (3D ICs) , 2009, 2009 Asia and South Pacific Design Automation Conference.

[11]  Alberto García Ortiz,et al.  Macro-3D: A Physical Design Methodology for Face-to-Face-Stacked Heterogeneous 3D ICs , 2020, 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[12]  Sung Kyu Lim,et al.  How much cost reduction justifies the adoption of monolithic 3D ICs at 7nm node? , 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).