MeXT: A Flow for Multiprocessor Exploration

This paper presents an extended design approach for heterogeneous multiprocessor systems. The goal in this particular design exploration approach is to ease the implementation of an adaptive multiprocessor system by creating components such as processing nodes or memories from an application. A program is profiled and analysed to gather information about task precedence, communication cost or computational patterns for hardware accelerator generation. This information is then used to solve an optimization problem using Integer Linear Programming or Answer Set Programming with the goal of 1) creating suitable multiprocessor hardware architecture and 2) mapping of tasks onto the processors. A lightweight message-passing library for on-chip communication of parallel programs is provided. The resulting abstract architecture is further processed using the vendor tool-chain to generate the target platform’s configuration. Two real-world case studies are used to show the feasibility of our design-space exploration approach.

[1]  Bruce K. Holmer Automatic Design of Computer Instruction Sets , 1993 .

[2]  Scott A. Mahlke,et al.  Modulo graph embedding: mapping applications onto coarse-grained reconfigurable architectures , 2006, CASES '06.

[3]  Rakesh Kumar,et al.  Magellan: A Search and Machine Learning-based Framework for Fast Multi-core Design Space Exploration and Optimization , 2008, 2008 Design, Automation and Test in Europe.

[4]  Ing-Jer Huang,et al.  Synthesis of application specific instruction sets , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Jason Cong,et al.  Pattern-based behavior synthesis for FPGA resource reduction , 2008, FPGA '08.

[6]  Christophe Bobda,et al.  FLexiTASK: A Flexible FPGA Overlay for Efficient Multitasking , 2018, ACM Great Lakes Symposium on VLSI.

[7]  Karthikeyan Sankaralingam,et al.  Dark Silicon and the End of Multicore Scaling , 2012, IEEE Micro.

[8]  Koen Bertels,et al.  The Instruction-Set Extension Problem: A Survey , 2008, ARC.

[9]  Hugo De Man,et al.  Instruction set definition and instruction selection for ASIPs , 1994, Proceedings of 7th International Symposium on High-Level Synthesis.

[10]  Ludovic Apvrille,et al.  Evaluation of ASIPs Design with LISATek , 2008, SAMOS.

[11]  Majid Sarrafzadeh,et al.  Instruction generation for hybrid reconfigurable systems , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[12]  Giovanni De Micheli,et al.  Automatic instruction set extension and utilization for embedded processors , 2003, Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors. ASAP 2003.

[13]  Rainer Leupers,et al.  Instruction set extraction from programmable structures , 1994, EURO-DAC '94.

[14]  Christophe Bobda,et al.  Makespan minimization in automatic synthesis of multiprocessor systems from parallel programs , 2008, 2008 International Conference on Field-Programmable Technology.

[15]  Chen Dong,et al.  A Coarse-Grained Reconfigurable Architecture with Compilation for High Performance , 2012, Int. J. Reconfigurable Comput..

[16]  John P. Knight,et al.  Physical resource binding for a coarse-grain reconfigurable array using evolutionary algorithms , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[17]  Paul Chow,et al.  TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAs , 2006, 2006 International Conference on Field Programmable Logic and Applications.

[18]  Wayne H. Wolf,et al.  The future of multiprocessor systems-on-chips , 2004, Proceedings. 41st Design Automation Conference, 2004..

[19]  Anshul Kumar,et al.  Automatic synthesis of system on chip multiprocessor architectures for process networks , 2004, CODES+ISSS '04.

[20]  Stamatis Vassiliadis,et al.  Automatic selection of application-specific instruction-set extensions , 2006, Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06).

[21]  Luca Benini,et al.  NoC synthesis flow for customized domain specific multiprocessor systems-on-chip , 2005, IEEE Transactions on Parallel and Distributed Systems.

[22]  Donald E. Thomas,et al.  Rethinking Automated Synthesis of MPSoC Architectures , 2007, 2007 IEEE International Parallel and Distributed Processing Symposium.

[23]  Christophe Bobda,et al.  SoC-MPI: A Flexible Message Passing Library for Multiprocessor Systems-on-Chips , 2008, 2008 International Conference on Reconfigurable Computing and FPGAs.

[24]  Fernando Gehm Moraes,et al.  Architectural Issues in Homogeneous NoC-Based MPSoC , 2007, 18th IEEE/IFIP International Workshop on Rapid System Prototyping (RSP '07).