Timing Models for MOS Circuits

Performance is an important aspect of integrated circuit design, and depends in part on the speed of the underlying circuits. This thesis presents a new method of analyzing MOS circuit delay, based on a single-time-constant approximation. The timing models characterize the circuit by a single parameter, which depends on the resistance and capacitance of the circuit elements. To ensure the single- time-constant approximation is valid for a particular circuit, the timing models provide both an estimate and bounds for the output waveform. For circuits where the bounds are poor, an improved timing model is derived. These simple models provide insight about circuit performance issues, as well as determining the circuit delay. The timing models are first developed for linear networks and then are extended to model MOS circuits driven by a step input. By using the single-time-constant approximation, the output waveform of a complex MOS circuit can be modelled by the output of a circuit consisting of a single MOS transistor and a single capacitor. Finally, a new circuit model of a gate is used to derive the output waveform of a circuit driven by an arbitrary input. The resulting timing model does not depend strongly on the shape of the input: the output waveform only depends on the input''s slope at the gate''s switching voltage.

[1]  Albert Malvino,et al.  Electronic Principles , 1979 .

[2]  David J. Pilling,et al.  Computer-aided prediction of delays in LSI logic systems , 1973, DAC '73.

[3]  Stephen A. Szygenda,et al.  Proceedings of the 15th Design Automation Conference , 1976, DAC 1978.

[4]  A.L. Sangiovanni-Vincentelli,et al.  A survey of third-generation simulation techniques , 1981, Proceedings of the IEEE.

[5]  Michael Monachino Design Verification System for Large-Scale LSI Designs , 1982, 19th Design Automation Conference.

[6]  W. C. Elmore The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers , 1948 .

[7]  Mark Horowitz,et al.  Resistance Extraction from Mask Layout Data , 1983, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Richard D. Thornton,et al.  Multistage Transistor Circuits , 1965 .

[9]  Rathin Putatunda Auto-Delay: A Program for Automatic Calculation of Delay in LSI/VLSI Chips , 1982, DAC 1982.

[10]  Theodore I. Kamins,et al.  Device Electronics for Integrated Circuits , 1977 .

[11]  Lynn Conway,et al.  Introduction to VLSI systems , 1978 .

[12]  Kaoru Okazaki,et al.  A Multiple Media Delay Simulator for MOS LSI Circuits , 1983, 20th Design Automation Conference Proceedings.

[13]  Basant R. Chawla,et al.  Motis - an mos timing simulator , 1975 .

[14]  A. Jimenez,et al.  Algorithms for ASTAP--A network-analysis program , 1973 .

[15]  M.L. Liou,et al.  Computer-aided analysis of electronic circuits: Algorithms and computational techniques , 1977, Proceedings of the IEEE.

[16]  T. I. Kirkpatrick,et al.  PERT as an aid to logic design , 1966 .

[17]  Rathin Putatunda,et al.  Auto-Delay: A Program for Automatic Calculation of Delay in LSI/VLSI Chips , 1982, 19th Design Automation Conference.

[18]  Albert E. Ruehli,et al.  Macromodeling-An Approach for Analyzing Large-Scale Circuits , 1974 .

[19]  John K. Ousterhout Crystal: a Timing Analyzer for nMOS VLSI Circuits , 1983 .

[20]  Paul Penfield,et al.  Signal Delay in RC Tree Networks , 1981, 18th Design Automation Conference.

[21]  Mark Horowitz,et al.  Signal Delay in RC Tree Networks , 1983, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[22]  Norman P. Jouppi,et al.  TV: An nMOS Timing Analyzer , 1983 .