Subsets of Primary Input Vectors in Sequential Test Generation for Single Stuck-at Faults

The complexity of deterministic sequential test generation for a target fault in a circuit with n primary inputs is determined by the need to explore a search space that consists of 2n primary input vectors at every time unit. This paper studies the possibility of reducing the complexity of deterministic sequential test generation by using subsets of primary input vectors of limited sizes during test generation for target faults. It considers a test generation procedure that uses subsets of primary input vectors of size N, for increasing values of N starting with N=1 . The subsets consist of primary input vectors from the test sequence already generated, and of random primary input vectors. The results indicate that all or most of the detectable single stuck-at faults in benchmark circuits can be detected using small subsets of primary input vectors.

[1]  Daniel G. Saab,et al.  Iterative simulation-based Genetics + Deterministic Techniques = Complete AtPG , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[2]  Thomas J. Snethen.  Simulator-oriented fault test generator , 1988, 25 years of DAC.

[3]  Prathima Agrawal,et al.  A directed search method for test generation using a concurrent simulator , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[4]  Robert C. Aitken,et al.  IDDQ and AC scan: the war against unmodelled defects , 1996, Proceedings International Test Conference 1996. Test and Design Validity.

[5]  Ralph A. Marlett.  An Effective Test Generation System for Sequential Circuits , 1986, DAC 1986.

[6]  Kenneth M. Butler,et al.  A case study of ir-drop in structured at-speed testing , 2003, International Test Conference, 2003. Proceedings. ITC 2003..

[7]  Irith Pomeranz,et al.  On generating compact test sequences for synchronous sequential circuits , 1995, Proceedings of EURO-DAC. European Design Automation Conference.

[8]  Janak H. Patel,et al.  HITEC: a test generation package for sequential circuits , 1991, Proceedings of the European Conference on Design Automation..

[9]  Paolo Prinetto,et al.  Advanced techniques for GA-based sequential ATPGs , 1996, Proceedings ED&TC European Design and Test Conference.

[10]  Jeff Rearick.  Too much delay fault coverage is a bad thing , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).

[11]  Wu-Tung Cheng,et al.  Gentest: an automatic test-generation system for sequential circuits , 1989, Computer.

[12]  Kewal K. Saluja,et al.  Fast test generation for sequential circuits , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[13]  Irith Pomeranz,et al.  Primary Input Vectors to Avoid in Random Test Sequences for Synchronous Sequential Circuits , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[14]  Irith Pomeranz,et al.  PROPTEST: a property-based test generator for synchronous sequential circuits , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  Irith Pomeranz,et al.  TOV: Sequential Test Generation by Ordering of Test Vectors , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[16]  Irith Pomeranz,et al.  Techniques for improving the efficiency of sequential circuit test generation , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

[17]  Irith Pomeranz,et al.  Input Cubes with Lingering Synchronization Effects and their Use in Random Sequential Test Generation , 2009, 2009 14th IEEE European Test Symposium.

[18]  Michael S. Hsiao,et al.  Sequential circuit test generation using dynamic state traversal , 1997, Proceedings European Design and Test Conference. ED & TC 97.