A parameterized VHDL library for on-line testing

We describe a library of parameterized VHDL models for various concurrent fault detection circuits and maintenance functions developed for simulation and synthesis of ASICs which support on-line testing and diagnostics in systems designed for high reliability and availability. Issues associated with the selection and modeling of the various online testing functions are also discussed.

[1]  Dhiraj K. Pradhan,et al.  Error-Control Techniques for Logic Processors , 1972, IEEE Transactions on Computers.

[2]  Barry W. Johnson Design & analysis of fault tolerant digital systems , 1988 .

[3]  Algirdas Avizienis,et al.  The STAR (Self-Testing And Repairing) Computer: An Investigation of the Theory and Practice of Fault-Tolerant Computer Design , 1971, IEEE Transactions on Computers.

[4]  Niraj K. Jha,et al.  Design and synthesis of self-checking VLSI circuits , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Michael Nicolaidis,et al.  Fault-Secure Parity Prediction Arithmetic Operators , 1997, IEEE Des. Test Comput..

[6]  W. W. Peterson,et al.  Error-Correcting Codes. , 1962 .

[7]  Michael Nicolaidis,et al.  A tool for automatic generation of self-checking data paths , 1995, Proceedings 13th IEEE VLSI Test Symposium.

[8]  Rodham E. Tulloss,et al.  The Test Access Port and Boundary Scan Architecture , 1990 .

[9]  Charles E. Stroud,et al.  Multiple error detection and identification via signature analysis , 1995, J. Electron. Test..

[10]  Yervant Zorian,et al.  Fault-secure shifter design: results and implementations , 1997, Proceedings European Design and Test Conference. ED & TC 97.

[11]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[12]  Suchai Thanawastien,et al.  An SFS Berger check prediction ALU and its application to self-checking processor designs , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Edward J. McCluskey,et al.  Concurrent Error Detection and Testing for Large PLA's , 1982 .

[14]  Parag K. Lala,et al.  Fault tolerant and fault testable hardware design , 1985 .

[15]  E.J. McCluskey,et al.  Concurrent error detection and testing for large PLA's , 1982, IEEE Transactions on Electron Devices.

[16]  Prithviraj Banerjee,et al.  RSYN: a system for automated synthesis of reliable multilevel circuits , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[17]  Donatella Sciuto,et al.  Synthesis of multi-level self-checking logic , 1994, IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems.