Variation Aware Compilation for Improving Energy-Efficiency of Nanometer Processor Caches

[1]  ファラー ファーザン,et al.  A Code Placement Technique for Improving the Performance Yield of Processors with Defective Caches , 2005 .

[2]  Hiroto Yasuura,et al.  A Software Technique to Improve Yield of Processor Chips in Presence of Ultra-Leaky SRAM Cells Caused by Process Variation , 2007, 2007 Asia and South Pacific Design Automation Conference.

[3]  Tohru Ishihara,et al.  A non-uniform cache architecture for low power system design , 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..