A 35 ns 2K x 8 HMOS static RAM

This paper describes the circuit design and process techniques used to produce a 35-ns 2K /spl times/ 8 HMOS static RAM aimed at future high-end microprocessor applications. The circuit design uses predecoding of the row and column decoder/driver circuits to reduce active power, address-transition detection schemes to equalize internal nodes, and dynamic depletion-mode configurations for increased drive and speed. The technology is 2.5-3.0-/spl mu/m design rule HMOS employing an L/SUB eff/ of 1.7 /spl mu/m, t/SUB ox/=400 /spl Aring/, double-poly resistor loads, RIE and plasma etching, and wafer-stepper lithography. Using these techniques an access time of 35 ns, dc active power of 65 mA, standby power of 14 mA, and die size of 37.5K mil/SUP 2/ has been achieved. The cell size is 728 /spl mu/m/SUP 2/.

[1]  W.L. Martino,et al.  An on-chip back-bias generator for MOS dynamic memory , 1980, IEEE Journal of Solid-State Circuits.

[2]  J.J. Barnes,et al.  A 100 ns 5 V only 64Kx1 MOS dynamic RAM , 1980, IEEE Journal of Solid-State Circuits.

[3]  B. Ashmore,et al.  A 30 ns 16Kx1 fully static RAM , 1981, IEEE Journal of Solid-State Circuits.

[4]  F. Masuoka,et al.  A high speed 2k × 8 bit NMOS static RAM with a new double poly-Si gate memory cell process , 1980, 1980 International Electron Devices Meeting.

[5]  A. Ebel,et al.  A 25ns 4K static RAM , 1979, 1979 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[6]  K.C. Hardee,et al.  A fault-tolerant 30 ns/375 mW 16Kx1 NMOS static RAM , 1981, IEEE Journal of Solid-State Circuits.