Scaling trends in adiabatic logic

Adiabatic circuits which are able to dissipate less energy than the fundamental limit of static CMOS are promising candidates for low-power circuits in the frequency range in which signals are digitally processed. This paper shows the main sources of the energy dissipation in adiabatic circuits. It will be presented that with state-of-the-art transistors the distinction between quasi- and fully adiabatic circuits has become obsolete. With the shrinking of the transistor dimensions, new leakage mechanisms like gate leakage occur. As the adiabatic circuits work with an oscillating power supply, leakage currents flow only a part of the period. Without any further effort adiabatic circuits save about 30% of energy dissipation caused by leakage. As in static CMOS, adiabatic circuits benefit from voltage scaling. The Efficient Charge Recovery Logic scales linearly down to supply voltages near the threshold voltage. Simulations with a sinusoidal power supply showed no significant difference to a trapezoidal supply at most frequencies. For overall dissipation accounting also for generator efficiency and attenuation on the wiring, the sinusoidal supply voltage should be preferred

[1]  Massoud Pedram,et al.  Low power design methodologies , 1996 .

[2]  Roberto Saletti,et al.  Simple model for positive-feedback adiabatic logic power consumption estimation , 2000 .

[3]  D. Schmitt-Landsiedel,et al.  An ultra low-power adiabatic adder embedded in a standard 0.13/spl mu/m CMOS environment , 2003, ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705).

[4]  Soo-Ik Chae,et al.  nMOS reversible energy recovery logic for ultra-low-energy applications , 2000, IEEE Journal of Solid-State Circuits.

[5]  Anantha P. Chandrakasan,et al.  Low Power Digital CMOS Design , 1995 .

[6]  D. Schmitt-Landsiedel,et al.  Sleep transistor circuits for fine-grained power switch-off with short power-down times , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[7]  Anantha Chandrakasan,et al.  Scaling of stack effect and its application for leakage reduction , 2001, ISLPED'01: Proceedings of the 2001 International Symposium on Low Power Electronics and Design (IEEE Cat. No.01TH8581).

[8]  D. Schmitt-Landsiedel,et al.  Adiabatic 4-bit adders: comparison of performance and robustness against technology parameter variations , 2002, The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002..

[9]  C. Hu,et al.  Hole injection oxide breakdown model for very low voltage lifetime extrapolation , 1993, 31st Annual Proceedings Reliability Physics 1993.

[10]  C. Hu,et al.  Hole injection SiO/sub 2/ breakdown model for very low voltage lifetime extrapolation , 1994 .

[11]  Suhwan Kim,et al.  Single-phase source-coupled adiabatic logic , 1999, ISLPED '99.

[12]  Deog-Kyoon Jeong,et al.  An efficient charge recovery logic circuit , 1996, IEEE J. Solid State Circuits.

[13]  Vojin G. Oklobdzija,et al.  Pass-transistor adiabatic logic using single power-clock supply , 1997 .

[14]  Randall L. Geiger,et al.  VLSI Design Techniques for Analog and Digital Circuits , 1989 .

[15]  Vojin G. Oklobdzija,et al.  Clocked CMOS Adiabatic Logic with Single AC Power Supply , 1995, ESSCIRC '95: Twenty-first European Solid-State Circuits Conference.